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cache_impl.hh
Age
Commit message (
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Author
2015-02-11
mem: remove redundant test in in Cache::recvTimingResp()
Steve Reinhardt
2015-02-11
mem: add local var in Cache::recvTimingResp()
Steve Reinhardt
2015-03-14
mem: clean up write buffer check in Cache::handleSnoop()
Steve Reinhardt
2015-03-02
mem: Unify all cache DPRINTF address formatting
Andreas Hansson
2015-03-02
mem: Fix cache MSHR conflict determination
Andreas Hansson
2015-03-02
mem: Add option to force in-order insertion in PacketQueue
Stephan Diestelhorst
2015-03-02
mem: Downstream components consumes new crossbar delays
Marco Balboni
2015-03-02
mem: Tidy up the cache debug messages
Andreas Hansson
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2015-03-02
mem: Fix prefetchSquash + memInhibitAsserted bug
Ali Jafri
2015-02-11
mem: Clarification of packet crossbar timings
Marco Balboni
2015-02-11
mem: Clarify usage of latency in the cache
Marco Balboni
2015-02-03
mem: Clarify express snoop behaviour
Andreas Hansson
2015-02-03
mem: Clarify cache behaviour for pending dirty responses
Andreas Hansson
2015-01-22
mem: Remove Packet source from ForwardResponseRecord
Andreas Hansson
2015-01-20
mem: Fix bug in cache request retry mechanism
Andreas Hansson
2014-12-23
mem: Fix event scheduling issue for prefetches
Mitch Hayenga
2014-12-23
mem: Fix bug relating to writebacks and prefetches
Mitch Hayenga
2014-12-23
mem: Rework the structuring of the prefetchers
Mitch Hayenga
2014-12-23
mem: Add parameter to reserve MSHR entries for demand access
Mitch Hayenga
2014-12-02
mem: Support WriteInvalidate (again)
Curtis Dunham
2014-12-02
mem: Remove WriteInvalidate support
Curtis Dunham
2014-12-02
mem: Clean up packet data allocation
Andreas Hansson
2014-12-02
mem: Cleanup Packet::checkFunctional and hasData usage
Andreas Hansson
2014-12-02
mem: Make the requests carried by packets const
Andreas Hansson
2014-12-02
mem: Add checks and explanation for assertMemInhibit usage
Andreas Hansson
2014-12-02
mem: Remove redundant Packet::allocate calls
Andreas Hansson
2014-12-02
mem: Add const getters for write packet data
Andreas Hansson
2014-10-21
mem: don't inhibit WriteInv's or defer snoops on their MSHRs
Curtis Dunham
2014-10-29
mem: have WriteInvalidate obsolete MSHRs
Curtis Dunham
2014-10-09
mem: Add packet sanity checks to cache and MSHRs
Andreas Hansson
2014-09-27
misc: Fix a bunch of minor issues identified by static analysis
Andreas Hansson
2014-09-20
mem: Rename Bus to XBar to better reflect its behaviour
Andreas Hansson
2014-09-19
mem: Add checks to sendTimingReq in cache
Andreas Hansson
2014-06-27
mem: write streaming support via WriteInvalidate promotion
Curtis Dunham
2014-09-03
mem: Fix a bug in the cache port flow control
Andreas Hansson
2014-05-13
cpu, mem: Make software prefetches non-blocking
Curtis Dunham
2014-09-03
cache: Fix handling of LL/SC requests under contention
Geoffrey Blake
2014-08-13
mem: Properly set cache block status fields on writebacks
Mitch Hayenga
2014-05-09
mem: Squash prefetch requests from downstream caches
Mitch Hayenga
2014-03-07
mem: Fix incorrect assert failure in the Cache
Prakash Ramrakhyani
2014-02-18
mem: Filter cache snoops based on address ranges
Andreas Hansson
2014-01-29
mem: prefetcher: add options, support for unaligned addresses
Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-28
mem: Remove redundant findVictim() input argument
Amin Farmahini
2014-01-24
mem: Add support for a security bit in the memory system
Giacomo Gabrielli
2014-01-24
mem: per-thread cache occupancy and per-block ages
Dam Sunwoo
2013-10-17
cpu: add consistent guarding to *_impl.hh files.
Matt Horsnell
2013-07-18
mem: Add cache class destructor to avoid memory leaks
Xiangyu Dong
2013-06-27
mem: Reorganize cache tags and make them a SimObject
Prakash Ramrakhyani
2013-06-27
mem: Align cache timing to clock edges
Andreas Hansson
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