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2006-10-22s/pktuest/request/ (all in comments)Steve Reinhardt
--HG-- extra : convert_revision : 7ce779242a15245a20322c0b6c40d02c8ddd15ad
2006-10-20Use PacketPtr everywhereNathan Binkert
--HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-18Get rid of obsolete in-cache copy support.Steve Reinhardt
--HG-- extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
2006-10-17Fixes to cache eliminating the assumption that the Packet is still valid ↵Ron Dreslinski
after sending out a request. Still need to rework upgrades into this system, but works for now. src/mem/cache/base_cache.cc: Re order code to be more readable src/mem/cache/base_cache.hh: Be sure to delete the copy on a bus block src/mem/cache/cache_impl.hh: Be sure to remove the copy on a writeback success src/mem/cache/miss/mshr_queue.cc: Demorgans to make it easier to understand src/mem/tport.cc: Delete writebacks --HG-- extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
2006-10-12Fix problems with unCacheable addresses in timing-coherenceRon Dreslinski
src/base/traceflags.py: src/mem/physical.cc: Add debug falgs fro physical memory accesses src/mem/cache/cache_impl.hh: Snoops to uncacheable blocks should not happen src/mem/cache/miss/miss_queue.cc: Set the size properly on unCacheable accesses --HG-- extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
2006-10-10Fix some more mem leaks, still some leftRon Dreslinski
Update retry mechanism src/mem/cache/base_cache.cc: Rework the retry mechanism src/mem/cache/base_cache.hh: Rework the retry mechanism Try to fix memory bug src/mem/cache/cache_impl.hh: Rework upgrades to not be blocked by slave src/mem/cache/miss/mshr_queue.cc: Fix mem leak on writebacks --HG-- extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
2006-10-10Fix several bugs pertaining to upgrades/mem leaks.Ron Dreslinski
src/mem/cache/base_cache.cc: Fix a bug about not having a request to send src/mem/cache/base_cache.hh: Fix a bug with the blocking code src/mem/cache/cache.hh: AFix a bug with snoop hits in WB buffer src/mem/cache/cache_impl.hh: Fix a bug with snoop hits in WB buffer Also, add better DPRINTF's src/mem/cache/miss/miss_queue.cc: Fix a bug with upgrades (Need to clean it up later) src/mem/cache/miss/mshr.cc: Fix a memory leak bug, still some outstanding with writebacks not being deleted src/mem/cache/miss/mshr_queue.cc: Fix a bug about upgrades (need to clean up later) src/mem/packet.hh: Fix for newly added cmd attribute for upgrades tests/configs/memtest.py: More interesting testcase --HG-- extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
2006-10-09Set size properly on uncache accessesRon Dreslinski
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.hh: Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct --HG-- extra : convert_revision : 2e8e812bf7fd3ba2b4cba7f7173cb41862f761af
2006-10-07Fix infinite writebacks bug in cache.Ron Dreslinski
src/mem/cache/cache_impl.hh: Make sure to pop the list. Fixes infinite writeback bug. src/mem/cache/miss/mshr_queue.cc: Add an assert as sanity check in case .full() stops working again. --HG-- extra : convert_revision : d847e49a397eeb0b7c5ac060fcfc3eaeac921311
2006-10-06Another thread number removedRon Dreslinski
--HG-- extra : convert_revision : 4cfb83b8162745d686e8697f29f74f37b1a71525
2006-10-06Remove threadnum from cache everywhere for nowRon Dreslinski
Fix so that blocking for the same reason doesn't fail. I.E. multiple writebacks want to set the blocked flag. src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/mshr.cc: Remove threadnum from cache everywhere for now --HG-- extra : convert_revision : 7890712147655280b4f1439d486feafbd5b18b2b
2006-08-15Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/tmp/m5.newmem --HG-- extra : convert_revision : d490a68eeabd0da7cd9791e14ca3678ed0fd31e6
2006-08-15fixes for gcc 4.1Ali Saidi
Nate needs to fix sinic builder stuff Gabe needs to verify my fixes to decoder.isa OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset README: Fix the swig version in the readme src/SConscript: remove sinic until nate fixes the builder crap for it src/arch/alpha/system.hh: src/arch/mips/isa/includes.isa: src/arch/sparc/isa/decoder.isa: src/base/stats/visit.cc: src/base/timebuf.hh: src/dev/ide_disk.cc: src/dev/sinic.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr_queue.cc: src/mem/packet.hh: src/mem/request.hh: src/sim/builder.hh: src/sim/system.hh: fixes for gcc 4.1 --HG-- extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
2006-08-15Pulled out changes to fix EIO programs with caches. Also fixes any ↵Ron Dreslinski
translatingPort read/write Blob function problems with caches. -Basically removed the ASID from places it is no longer needed due to PageTable src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/miss_queue.hh: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/prefetch/base_prefetcher.hh: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: Remove asid where it wasn't neccesary anymore due to Page Table --HG-- extra : convert_revision : ab8bbf4cc47b9eaefa9cdfa790881a21d0e7bf28
2006-08-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ewok.(none):/home/gblack/m5/newmem src/cpu/static_inst.hh: SCCS merged --HG-- extra : convert_revision : a4f6377dbd691ab58fe5f7958b983b092575f250
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
--HG-- extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
2006-08-14Fix up doxygen.Steve Reinhardt
--HG-- rename : docs/footer.html => src/doxygen/footer.html rename : docs/stl.hh => src/doxygen/stl.hh extra : convert_revision : 2b2e5637930843c1be07deaa708fd4126213cda2
2006-07-10Some fixes so that MSHR's are matched and we don't issue overlapping ↵Ron Dreslinski
requests with detailed cpu src/mem/cache/base_cache.cc: If we still have outstanding requests, need to schedule event again src/mem/cache/miss/miss_queue.cc: Need to use block size so overlapping requests match in the MSHR's src/mem/cache/miss/mshr.cc: Actually save the address, otherwise we can't match MSHR's --HG-- extra : convert_revision : f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
2006-07-05Fix some unset values in the request in the timing CPU.Ron Dreslinski
Properly implement the MSHR allocate function. src/cpu/simple/timing.cc: Set the thread context in the CPU. Need to do this properly, currently I just set it to Cpu=0 Thread=0. This will just cause all the stats in the cache based on these to just yield totals and not a distribution. src/mem/cache/miss/mshr.cc: Properly implement the allocate function for the MSHR. --HG-- extra : convert_revision : bcece518e54ed1404db3196f996a77b4dd5c1c1e
2006-06-30First pass, now compiles with current head of tree.Ron Dreslinski
Compile and initialization work, still working on functionality. src/mem/cache/base_cache.cc: Temp fix for cpu's use of getPort functionality. CPU's will need to be ported to the new connector objects. Also, all packets have to have data or the delete fails. src/mem/cache/cache.hh: Fix function prototypes so overloading works src/mem/cache/cache_impl.hh: fix functions to match virtual base class src/mem/cache/miss/miss_queue.cc: Packets havve to have data, or delete fails src/python/m5/objects/BaseCache.py: Update for newmem --HG-- extra : convert_revision : 2b6ad1e9d8ae07ace9294cd257e2ccc0024b7fcb
2006-06-30Fix the packet data allocation methods. Small fixes from changesets after ↵Ron Dreslinski
my initial work. This now compiles. src/mem/cache/base_cache.cc: Fix getPort function that changed src/mem/cache/base_cache.hh: Fix get port function, provide default implementations of virtual functions in the base class src/mem/cache/cache.hh: Fix virtual function declerations src/mem/cache/cache_builder.cc: Fix params src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/iic.cc: src/mem/cache/tags/lru.cc: Properly allocate data in packet --HG-- extra : convert_revision : dedf8b0f76ab90b06b60f8fe079c0ae361f91a48
2006-06-29Still missing prefetch and tags directories as well as cache builder.Ron Dreslinski
Some implementation details were left blank still, need to fill them in. src/SConscript: Reorder build to compile all files first src/mem/cache/cache.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: More changesets pulled, now compiles everything in /miss directory and in the root directory src/mem/packet.hh: Add some more support, need to clean some of it out once everything is working --HG-- extra : convert_revision : ba73676165810edf2c2effaf5fbad8397d6bd800
2006-06-28More Changes, working towards cache.cc compiling. Headers cleaned up.Ron Dreslinski
src/mem/cache/cache_blk.hh: Remove XC --HG-- extra : convert_revision : aa2c43e4412ebb93165e12f693d5126983cfd0dc
2006-06-28Backing in more changsets, getting closer to compileRon Dreslinski
base_cache.cc compiles, continuing on src/SConscript: Add in compilation flags for cache files src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: Back in more fixes, now base_cache compiles src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/miss_queue.hh: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/iic.cc: src/mem/cache/tags/lru.cc: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lru.cc: src/mem/packet.cc: src/mem/packet.hh: src/mem/request.hh: Backing in more changsets, getting closer to compile --HG-- extra : convert_revision : ac2dcda39f8d27baffc4db1df17b9a1fcce5b6ed
2006-06-28Was having difficulty with merging the cache, reverted to an early version ↵Ron Dreslinski
and will add back in the patches to make it work soon. src/mem/cache/prefetch/tagged_prefetcher_impl.hh: Trying to merge src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.cc: src/mem/cache/miss/miss_queue.hh: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/prefetch/base_prefetcher.hh: src/mem/cache/prefetch/ghb_prefetcher.cc: src/mem/cache/prefetch/ghb_prefetcher.hh: src/mem/cache/prefetch/stride_prefetcher.cc: src/mem/cache/prefetch/stride_prefetcher.hh: src/mem/cache/prefetch/tagged_prefetcher.hh: src/mem/cache/tags/base_tags.cc: src/mem/cache/tags/base_tags.hh: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/repl/gen.cc: src/mem/cache/tags/repl/gen.hh: src/mem/cache/tags/repl/repl.cc: src/mem/cache/tags/repl/repl.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_blk.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: Pulling an early version of the cache into the tree due to merging issues. Will apply patches and push. --HG-- extra : convert_revision : 3276e5fb9a6272681a1690babf2b586dd0e1f380
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