gem5 - gem5

Age	Commit message (Collapse)	Author
2015-03-27	mem: Modernise MSHR iterators to C++11	Andreas Hansson
	This patch updates the iterators in the MSHR and MSHR queues to use C++11 range-based for loops. It also does a bit of additional house keeping.
2015-03-27	mem: Align all MSHR entries to block boundaries	Andreas Hansson
	This patch aligns all MSHR queue entries to block boundaries to simplify checks for matches. Previously there were corner cases that could lead to existing entries not being identified as matches. There are, rather alarmingly, a few regressions that change with this patch.
2015-02-03	mem: Clarify cache behaviour for pending dirty responses	Andreas Hansson
	This patch adds a bit of clarification around the assumptions made in the cache when packets are sent out, and dirty responses are pending. As part of the change, the marking of an MSHR as in service is simplified slightly, and comments are added to explain what assumptions are made.
2014-12-02	mem: Remove WriteInvalidate support	Curtis Dunham
	Prepare for a different implementation following in the next patch
2014-10-21	mem: don't inhibit WriteInv's or defer snoops on their MSHRs	Curtis Dunham
	WriteInvalidate semantics depend on the unconditional writeback or they won't complete. Also, there's no point in deferring snoops on their MSHRs, as they don't get new data at the end of their life cycle the way other transactions do. Add comment in the cache about a minor inefficiency re: WriteInvalidate.
2014-10-29	mem: have WriteInvalidate obsolete MSHRs	Curtis Dunham
	Since WriteInvalidate directly writes into the cache, it can create tricky timing interleavings with reads and writes to the same cache line that haven't yet completed. This patch ensures that these requests, when completed, don't overwrite the newer data from the WriteInvalidate.
2014-01-24	mem: Add support for a security bit in the memory system	Giacomo Gabrielli
	This patch adds the basic building blocks required to support e.g. ARM TrustZone by discerning secure and non-secure memory accesses.
2013-05-30	mem: Spring cleaning of MSHR and MSHRQueue	Andreas Hansson
	This patch does some minor tidying up of the MSHR and MSHRQueue. The clean up started as part of some ad-hoc tracing and debugging, but seems worthwhile enough to go in as a separate patch. The highlights of the changes are reduced scoping (private) members where possible, avoiding redundant new/delete, and constructor initialisation to please static code analyzers.
2013-04-22	mem: Adding verbose debug output in the memory system	Uri Wiener
	This patch provides useful printouts throughut the memory system. This includes pretty-printed cache tags and function call messages (call-stack like).
2012-09-25	MEM: Put memory system document into doxygen	Djordje Kovacevic

2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
	This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2010-09-09	cache: coherence protocol enhancements & bug fixes	Steve Reinhardt
	Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes.
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert

2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert

2009-02-16	Fixes to get prefetching working again.	Steve Reinhardt
	Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too.
2008-11-10	Cache: Refactor packet forwarding a bit.	Steve Reinhardt
	Makes adding write-through operations easier.
2008-02-10	Rename cache files for brevity and consistency with rest of tree.	Steve Reinhardt
	--HG-- rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62