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path: root/src/mem/cache/noncoherent_cache.hh
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2018-12-05mem-cache: Remove writebacks parameter from serviceMSHRTargetsDaniel R. Carvalho
Change 8ba77ae8fc98a355082da2bd9fdc6ecf4928f725 introduced the writebacks parameter, but it was never used. Change-Id: I225e5b399de42d77c72fc0012d3dc93ef39b8853 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/14896 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-22mem-cache: Move evictBlock(CacheBlk*, PacketList&) to baseDaniel R. Carvalho
Move evictBlock(CacheBlk*, PacketList&) to base cache, as it is both sub-classes implementations are equal. Change-Id: I80fbd16813bfcc4938fb01ed76abe29b3f8b3018 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13656 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Restructure whole-line writes to simplify write mergingNikos Nikoleris
This patch changes how we deal with whole-line writes their responses. With these changes, we use the MSHR tracking to determine if a whole-line is written, and on a fill we simply handle the invalidation response, with the actual writes taking place as part of satisfying the CPU-side hit. Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b Reviewed-on: https://gem5-review.googlesource.com/c/12905 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-13mem-cache: Fix bug in handleAtomicReqMissNikos Nikoleris
"4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug where if an atomic request that fills in using the tempBlock it will not evict it when it finishes handling the request as it should. This triggers an assertion. This change fixes this bug. Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12644 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-31mem-cache: Add a non-coherent cacheNikos Nikoleris
The class re-uses the existing MSHR and write queue. At the moment every single access is handled by the cache, even uncacheable accesses, and nothing is forwarded. This is a modified version of a changeset put together by Andreas Hansson <andreas.hansson@arm.com> Change-Id: I41f7f9c2b8c7fa5ec23712a4446e8adb1c9a336a Reviewed-on: https://gem5-review.googlesource.com/8291 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>