index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
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log msg
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range
path:
root
/
src
/
mem
/
cache
/
prefetch
/
base.cc
Age
Commit message (
Expand
)
Author
2012-05-10
gem5: fix some iterator use and erase bugs
Ali Saidi
2012-04-14
MEM: Remove the Broadcast destination from the packet
Andreas Hansson
2012-02-12
mem: Add a master ID to each request object.
Ali Saidi
2012-02-12
prefetcher: Make prefetcher a sim object instead of it being a parameter on c...
Mrinmoy Ghosh
2011-09-01
Fix build for gcc-4.2 opt/fast
Lisa Hsu
2011-08-19
Prefetcher: Fix some memory leaks with the prefetcher.
Ali Saidi
2011-04-15
trace: reimplement the DTRACE function so it doesn't use a vector
Nathan Binkert
2011-04-15
includes: sort all includes
Nathan Binkert
2009-09-26
Force prefetches to check cache and MSHRs immediately prior to issue.
Steve Reinhardt
2009-09-23
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
Nathan Binkert
2009-04-20
request: rename INST_READ to INST_FETCH.
Steve Reinhardt
2009-02-16
Fixes to get prefetching working again.
Steve Reinhardt
2008-11-02
Add in Context IDs to the simulator. From now on, cpuId is almost never used,
Lisa Hsu
2008-02-10
Fix #include lines for renamed cache files.
Steve Reinhardt
2008-02-10
Rename cache files for brevity and consistency with rest of tree.
Steve Reinhardt