gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-09	misc: Fix a number of unitialised variables and members	Andreas Hansson
2014-09-03	arch: Cleanup unused ISA traits constants	Andreas Hansson
2014-01-29	mem: prefetcher: add options, support for unaligned addresses	Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-24	mem: Add support for a security bit in the memory system	Giacomo Gabrielli
2014-01-24	mem: per-thread cache occupancy and per-block ages	Dam Sunwoo
2013-02-19	mem: Add deferred packet class to prefetcher	Andreas Hansson
2013-02-19	sim: Make clock private and access using clockPeriod()	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-05-10	gem5: fix some iterator use and erase bugs	Ali Saidi
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2011-09-01	Fix build for gcc-4.2 opt/fast	Lisa Hsu
2011-08-19	Prefetcher: Fix some memory leaks with the prefetcher.	Ali Saidi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2009-09-26	Force prefetches to check cache and MSHRs immediately prior to issue.	Steve Reinhardt
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-04-20	request: rename INST_READ to INST_FETCH.	Steve Reinhardt
2009-02-16	Fixes to get prefetching working again.	Steve Reinhardt
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-02-10	Fix #include lines for renamed cache files.	Steve Reinhardt
2008-02-10	Rename cache files for brevity and consistency with rest of tree.	Steve Reinhardt