gem5 - gem5

Age	Commit message (Expand)	Author
2015-03-27	mem: Support any number of master-IDs in stride prefetcher	Stephan Diestelhorst
2014-12-23	mem: Change prefetcher to use random_mt	Mitch Hayenga
2014-12-23	mem: Rework the structuring of the prefetchers	Mitch Hayenga
2014-01-29	mem: Add additional tolerance to stride prefetcher	Mitch Hayenga
2014-01-29	mem: Allowed tagged instruction prefetching in stride prefetcher	Mitch Hayenga
2014-01-29	mem: prefetcher: add options, support for unaligned addresses	Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-24	mem: Add support for a security bit in the memory system	Giacomo Gabrielli
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2011-08-19	Prefetcher: Fix some memory leaks with the prefetcher.	Ali Saidi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2009-03-10	prefetch: don't panic on requests w/o contextID (e.g., writebacks).	Steve Reinhardt
2009-02-16	Fixes to get prefetching working again.	Steve Reinhardt
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-09-10	style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...	Ali Saidi
2008-02-10	Fix #include lines for renamed cache files.	Steve Reinhardt
2008-02-10	Rename cache files for brevity and consistency with rest of tree.	Steve Reinhardt