gem5 - gem5

Age	Commit message (Expand)	Author
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
2016-04-05	mem: Remove threadId from memory request class	Mitch Hayenga
2016-02-06	style: fix missing spaces in control statements	Steve Reinhardt
2015-10-12	misc: Remove redundant compiler-specific defines	Andreas Hansson
2015-07-30	mem: Remove unused RequestCause in cache	Andreas Hansson
2015-07-13	mem: Fix (ab)use of emplace to avoid temporary object creation	Andreas Hansson
2015-07-03	mem: Add clean evicts to improve snoop filter tracking	Ali Jafri
2015-03-27	mem: Support any number of master-IDs in stride prefetcher	Stephan Diestelhorst
2015-03-19	mem: Use emplace front/back for deferred packets	Andreas Hansson
2014-12-23	mem: Change prefetcher to use random_mt	Mitch Hayenga
2014-12-23	mem: Hide WriteInvalidate requests from prefetchers	Curtis Dunham
2014-12-23	mem: Rework the structuring of the prefetchers	Mitch Hayenga
2014-10-16	mem: Dynamically determine page bytes in memory components	Andreas Hansson
2014-09-20	mem: Remove the GHB prefetcher from the source tree	Mitch Hayenga
2014-09-09	misc: Fix a number of unitialised variables and members	Andreas Hansson
2014-09-03	arch: Cleanup unused ISA traits constants	Andreas Hansson
2014-01-29	mem: Add additional tolerance to stride prefetcher	Mitch Hayenga
2014-01-29	mem: Allowed tagged instruction prefetching in stride prefetcher	Mitch Hayenga
2014-01-29	mem: prefetcher: add options, support for unaligned addresses	Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-24	mem: Add support for a security bit in the memory system	Giacomo Gabrielli
2014-01-24	mem: per-thread cache occupancy and per-block ages	Dam Sunwoo
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson
2013-02-19	mem: Add deferred packet class to prefetcher	Andreas Hansson
2013-02-19	sim: Make clock private and access using clockPeriod()	Andreas Hansson
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-05-10	gem5: fix some iterator use and erase bugs	Ali Saidi
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2011-09-01	Fix build for gcc-4.2 opt/fast	Lisa Hsu
2011-08-19	Prefetcher: Fix some memory leaks with the prefetcher.	Ali Saidi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-02-23	Includes: Don't include isa_traits.hh and use the TheISA namespace unless rea...	Ali Saidi
2010-11-19	SCons: Support building without an ISA	Ali Saidi
2009-09-26	Force prefetches to check cache and MSHRs immediately prior to issue.	Steve Reinhardt
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2009-04-20	request: rename INST_READ to INST_FETCH.	Steve Reinhardt
2009-03-10	prefetch: don't panic on requests w/o contextID (e.g., writebacks).	Steve Reinhardt
2009-03-05	stats: Fix all stats usages to deal with template fixes	Nathan Binkert
2009-02-16	Fixes to get prefetching working again.	Steve Reinhardt
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-09-10	style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...	Ali Saidi
2008-02-10	Fix #include lines for renamed cache files.	Steve Reinhardt
2008-02-10	Rename cache files for brevity and consistency with rest of tree.	Steve Reinhardt
2007-08-30	params: Deprecate old-style constructors; update most SimObject constructors.	Miles Kaufmann
2007-06-21	Getting closer...	Steve Reinhardt
2007-06-17	More major reorg of cache. Seems to work for atomic mode now,	Steve Reinhardt