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path: root/src/mem/cache/prefetch
AgeCommit message (Expand)Author
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2015-10-12misc: Remove redundant compiler-specific definesAndreas Hansson
2015-07-30mem: Remove unused RequestCause in cacheAndreas Hansson
2015-07-13mem: Fix (ab)use of emplace to avoid temporary object creationAndreas Hansson
2015-07-03mem: Add clean evicts to improve snoop filter trackingAli Jafri
2015-03-27mem: Support any number of master-IDs in stride prefetcherStephan Diestelhorst
2015-03-19mem: Use emplace front/back for deferred packetsAndreas Hansson
2014-12-23mem: Change prefetcher to use random_mtMitch Hayenga
2014-12-23mem: Hide WriteInvalidate requests from prefetchersCurtis Dunham
2014-12-23mem: Rework the structuring of the prefetchersMitch Hayenga
2014-10-16mem: Dynamically determine page bytes in memory componentsAndreas Hansson
2014-09-20mem: Remove the GHB prefetcher from the source treeMitch Hayenga
2014-09-09misc: Fix a number of unitialised variables and membersAndreas Hansson
2014-09-03arch: Cleanup unused ISA traits constantsAndreas Hansson
2014-01-29mem: Add additional tolerance to stride prefetcherMitch Hayenga
2014-01-29mem: Allowed tagged instruction prefetching in stride prefetcherMitch Hayenga
2014-01-29mem: prefetcher: add options, support for unaligned addressesMitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-24mem: Add support for a security bit in the memory systemGiacomo Gabrielli
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-02-19mem: Add deferred packet class to prefetcherAndreas Hansson
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-05-10gem5: fix some iterator use and erase bugsAli Saidi
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2011-09-01Fix build for gcc-4.2 opt/fastLisa Hsu
2011-08-19Prefetcher: Fix some memory leaks with the prefetcher.Ali Saidi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-02-23Includes: Don't include isa_traits.hh and use the TheISA namespace unless rea...Ali Saidi
2010-11-19SCons: Support building without an ISAAli Saidi
2009-09-26Force prefetches to check cache and MSHRs immediately prior to issue.Steve Reinhardt
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-04-20request: rename INST_READ to INST_FETCH.Steve Reinhardt
2009-03-10prefetch: don't panic on requests w/o contextID (e.g., writebacks).Steve Reinhardt
2009-03-05stats: Fix all stats usages to deal with template fixesNathan Binkert
2009-02-16Fixes to get prefetching working again.Steve Reinhardt
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...Ali Saidi
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-06-21Getting closer...Steve Reinhardt
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt