| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2013-06-27 | mem: Reorganize cache tags and make them a SimObject | Prakash Ramrakhyani | |
| This patch reorganizes the cache tags to allow more flexibility to implement new replacement policies. The base tags class is now a clocked object so that derived classes can use a clock if they need one. Also having deriving from SimObject allows specialized Tag classes to be swapped in/out in .py files. The cache set is now templatized to allow it to contain customized cache blocks with additional informaiton. This involved moving code to the .hh file and removing cacheset.cc. The statistics belonging to the cache tags are now including ".tags" in their name. Hence, the stats need an update to reflect the change in naming. | |||
| 2012-06-29 | Cache: Fix the LRU policy for classic memory hierarchy | Lena Olson | |
| The LRU policy always evicted the least recently touched way, even if it contained valid data and another way was invalid, as can happen if a block has been invalidated by coherance. This can result in caches never warming up even though they are replacing blocks. This modifies the LRU policy to move blocks to LRU position on invalidation. | |||
| 2010-02-23 | cache: pull CacheSet out of LRU so that other tags can use associative sets. | Lisa Hsu | |
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |