Age | Commit message (Collapse) | Author |
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?? doesn't compile in warn statements
Should have been false, where I had a true.
src/cpu/o3/lsq_impl.hh:
Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
Forgot to signal atomic mode in snoopProbe
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extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
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Now to try L2 caches in FS.
src/mem/cache/base_cache.hh:
Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Properly forward invalidates in atomic/timing uni-coherence
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extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069
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src/mem/cache/cache_impl.hh:
Get the read data from the highest level of cache on a functional access
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extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
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configs/example/fs.py:
Add MOESI protocol to caches (uni coherence not quite working w/FS yet).
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extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
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Factor out some asserts that were on both
sides of an if/else.
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Reindent due to resulting changes in nesting.
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but not on zizzer... g++ 4 thing maybe?)
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extra : convert_revision : 31c49f1c55fe9daf6365411bfb5bb7f6ccc8032d
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Still a bug in atomic uni-coherence in FS.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
Only deallocate once
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extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
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after sending out a request.
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
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extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
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writebacks delete the packet.
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extra : convert_revision : 72b1c6296a16319f4d16c62bc7038365654dbc40
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sendTiming.
Still need to fix upgrades to use this path
src/mem/cache/base_cache.cc:
Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
Use copy of packet, because sendTiming may have changed the pkt
Also, delete the copy when the time comes
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extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : c3650273684f3fbdcd2e14e95d09ee3c6de8d6b6
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--HG--
extra : convert_revision : d5c0aadc35edf5c9495afcd3375f1f64716ef845
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Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)
Now both timing/atomic caches with MOESI in UP fail at same point.
src/dev/io_device.hh:
DMA's should send WriteInvalidates
src/mem/bridge.cc:
Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Fix CSHR's for flow control.
src/mem/packet.hh:
Make a writeInvalidateResp, since the DMA expects responses to it's writes
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extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
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extra : convert_revision : caa7664f6c945396fa38ce62fbda018ebed4eaa6
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src/mem/cache/base_cache.hh:
Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
Remove top level parameters from the cache
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extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
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The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?
src/mem/cache/base_cache.cc:
src/mem/tport.cc:
Add in functional check of retry queued packets.
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extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
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src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses
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extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
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src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.
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extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
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Fix bug with deadlocking
src/mem/cache/base_cache.cc:
Make sure to not wait anymore
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extra : convert_revision : 5f7b44a1c475820b9862275a0d6113ec2991735d
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src/mem/cache/base_cache.cc:
When turning asserts into if's don't forget to invert.
Must be too sleepy.
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extra : convert_revision : ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
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uprgades to owned blocks hit in the WB buffer
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extra : convert_revision : f0502836a79ce303150daa7e571badb0bce3a97a
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extra : convert_revision : 511c0bcd44b93d5499eefa8399f36ef8b6607311
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src/base/traceflags.py:
Add new flags for cacheport
src/mem/bus.cc:
Add debugging info
src/mem/cache/base_cache.cc:
Add debuggin info
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extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
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src/mem/cache/base_cache.cc:
Add sanity checks
src/mem/cache/base_cache.hh:
Fix for retry mechanism
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extra : convert_revision : 9298e32e64194b1ef3fe51242595eaa56dcbbcfd
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Update retry mechanism
src/mem/cache/base_cache.cc:
Rework the retry mechanism
src/mem/cache/base_cache.hh:
Rework the retry mechanism
Try to fix memory bug
src/mem/cache/cache_impl.hh:
Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
Fix mem leak on writebacks
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extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
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Fix Upgrades being blocked by slave
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extra : convert_revision : cca98a38e32233145163577500f1362cd807ab15
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/packet.hh:
Hand merge code
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extra : convert_revision : d659418f24f4f4bf9867fec8573a5d227c0dfcea
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src/mem/cache/base_cache.cc:
Fix a bug about not having a request to send
src/mem/cache/base_cache.hh:
Fix a bug with the blocking code
src/mem/cache/cache.hh:
AFix a bug with snoop hits in WB buffer
src/mem/cache/cache_impl.hh:
Fix a bug with snoop hits in WB buffer
Also, add better DPRINTF's
src/mem/cache/miss/miss_queue.cc:
Fix a bug with upgrades (Need to clean it up later)
src/mem/cache/miss/mshr.cc:
Fix a memory leak bug, still some outstanding with writebacks not being deleted
src/mem/cache/miss/mshr_queue.cc:
Fix a bug about upgrades (need to clean up later)
src/mem/packet.hh:
Fix for newly added cmd attribute for upgrades
tests/configs/memtest.py:
More interesting testcase
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extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
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Not fully implemented yet, but good enough for single level cache coherence
src/mem/packet.hh:
Add a bit to distinguish invalidates and upgrades
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extra : convert_revision : 5bf50d535857cea37fbdaf7993915d1332cb757e
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : 2adde42edead2cedeeba60cc0d2697a2d58682be
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Remove some dead code.
src/mem/cache/cache_impl.hh:
Upgrades don't need a response.
Moved satisfied check into bus so removed some dead code.
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/packet.hh:
Upgrades don't require a response
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extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
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src/cpu/memtest/memtest.cc:
Fix functional return path
src/cpu/memtest/memtest.hh:
Add snoop ranges in
src/mem/cache/base_cache.cc:
Properly signal NACKED
src/mem/cache/cache_impl.hh:
Catch nacked packet and panic for now
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extra : convert_revision : 59a64e82254dfa206681c5f987e6939167754d67
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
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extra : convert_revision : 8267487b935eaf11665841ace3a5c664751b53b0
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--HG--
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : b4cb1702ffa2fca298cfde47683cac019e1da900
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src/mem/cache/cache_impl.hh:
Add more usefull DPRINTF's
REmove the PC to get rid of asserts
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extra : convert_revision : 3f6d832b138d058dbe79bb5f42bd2db9c50b35b5
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Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/miss/blocking_buffer.hh:
src/mem/cache/miss/miss_queue.hh:
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct
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--HG--
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extra : convert_revision : a1558eb55806b2a3e7e63249601df2c143e2235d
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src/mem/cache/cache_impl.hh:
Fix a error case by putting a panic in.
Make sure to propogate sendFunctional calls with functional not atomic.
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extra : convert_revision : 05d03f729a40cfa3ecb68bcba172eb560b24e897
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
src/mem/bus.cc:
Hand merged. Needs to be fixed
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extra : convert_revision : df03219ccfd18431cc726a063bd29d30554944a1
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Fix an issue with memory handling writebacks.
src/mem/cache/base_cache.hh:
src/mem/tport.cc:
Only respond if the pkt needs a response.
src/mem/physical.cc:
Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.
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extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : f3067efb7f3ff30158d541dfc52de4ea8edae576
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code in general.
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