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path: root/src/mem/cache
AgeCommit message (Expand)Author
2015-03-02mem: Fix prefetchSquash + memInhibitAsserted bugAli Jafri
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
2015-02-03mem: Clarify express snoop behaviourAndreas Hansson
2015-02-03mem: Clarify cache behaviour for pending dirty responsesAndreas Hansson
2015-01-22mem: Remove Packet source from ForwardResponseRecordAndreas Hansson
2015-01-20mem: Fix bug in cache request retry mechanismAndreas Hansson
2014-12-23mem: Change prefetcher to use random_mtMitch Hayenga
2014-12-23mem: Hide WriteInvalidate requests from prefetchersCurtis Dunham
2014-12-23mem: Fix event scheduling issue for prefetchesMitch Hayenga
2014-12-23mem: Fix bug relating to writebacks and prefetchesMitch Hayenga
2014-12-23mem: Rework the structuring of the prefetchersMitch Hayenga
2014-12-23mem: Add parameter to reserve MSHR entries for demand accessMitch Hayenga
2014-12-02mem: Support WriteInvalidate (again)Curtis Dunham
2014-12-02mem: Remove WriteInvalidate supportCurtis Dunham
2014-12-02mem: Clean up packet data allocationAndreas Hansson
2014-12-02mem: Cleanup Packet::checkFunctional and hasData usageAndreas Hansson
2014-12-02mem: Make the requests carried by packets constAndreas Hansson
2014-12-02mem: Add checks and explanation for assertMemInhibit usageAndreas Hansson
2014-12-02mem: Remove redundant Packet::allocate callsAndreas Hansson
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-10-29arm, mem: Fix drain bug and provide drain prints for more components.Ali Saidi
2014-10-21mem: don't inhibit WriteInv's or defer snoops on their MSHRsCurtis Dunham
2014-10-29mem: have WriteInvalidate obsolete MSHRsCurtis Dunham
2014-10-16mem: Dynamically determine page bytes in memory componentsAndreas Hansson
2014-10-09mem: Add packet sanity checks to cache and MSHRsAndreas Hansson
2014-09-27misc: Fix a bunch of minor issues identified by static analysisAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20mem: Remove the GHB prefetcher from the source treeMitch Hayenga
2014-09-19misc: Remove assertions ensuring unsigned values >= 0Andreas Hansson
2014-09-19mem: Add checks to sendTimingReq in cacheAndreas Hansson
2014-09-09misc: Fix a number of unitialised variables and membersAndreas Hansson
2014-06-27mem: write streaming support via WriteInvalidate promotionCurtis Dunham
2014-09-03mem: Fix a bug in the cache port flow controlAndreas Hansson
2014-05-13cpu, mem: Make software prefetches non-blockingCurtis Dunham
2014-09-03cache: Fix handling of LL/SC requests under contentionGeoffrey Blake
2014-09-03arch: Cleanup unused ISA traits constantsAndreas Hansson
2014-08-13mem: Properly set cache block status fields on writebacksMitch Hayenga
2014-07-28mem: refactor LRU cache tags and add random replacement tagsAnthony Gutierrez
2014-05-09mem: Squash prefetch requests from downstream cachesMitch Hayenga
2014-04-01mem: Don't print out the data of a cache blockMitch Hayenga
2014-03-07mem: Fix incorrect assert failure in the CachePrakash Ramrakhyani
2014-02-18mem: Filter cache snoops based on address rangesAndreas Hansson
2014-01-29mem: Add additional tolerance to stride prefetcherMitch Hayenga
2014-01-29mem: Allowed tagged instruction prefetching in stride prefetcherMitch Hayenga
2014-01-29mem: prefetcher: add options, support for unaligned addressesMitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-28mem: Remove redundant findVictim() input argumentAmin Farmahini
2014-01-24mem: Add support for a security bit in the memory systemGiacomo Gabrielli
2014-01-24Cache: Collect very basic stats on tag and data accessesTimothy M. Jones
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
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