gem5 - gem5

Age	Commit message (Expand)	Author
2017-02-21	mem: Remove the unused asid field from the CacheBlk class	Nikos Nikoleris
2017-02-21	mem: Remove unused arguments (asid/contex_id) from accessBlock	Nikos Nikoleris
2017-02-21	mem: Remove unused type BlkList from the cache and the tags	Nikos Nikoleris
2017-02-21	mem: Remove unused functions from the tag classes	Nikos Nikoleris
2017-02-21	mem: Always use the helper function to invalidate a block	Nikos Nikoleris
2017-02-21	mem: Fix MSHR assert triggering for invalidated prefetches	Sascha Bischoff
2017-02-21	mem: Populate the secure flag in the writeback visitor	Nikos Nikoleris
2017-02-21	mem: Remove stale argument from a panic statement	Nikos Nikoleris
2017-02-19	sim: Ensure draining is deterministic	Andreas Hansson
2017-02-19	mem: Ensure deferred snoops are cache-line aligned	Andreas Hansson
2017-02-11	mem: fix printing of 1st cache tags line	Bjoern A. Zeeb
2016-11-09	style: [patch 3/22] reduce include dependencies in some headers	Brandon Potter
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2016-12-05	mem: Respond to InvalidateReq when the block is (pending) dirty	Nikos Nikoleris
2016-12-05	mem: Invalidate a blk when servicing the 1st invalidating target	Nikos Nikoleris
2016-12-05	mem: Allow non invalidating snoops on an InvalidateReq MSHR	Nikos Nikoleris
2016-12-05	mem: Always use InvalidateReq to service WriteLineReq misses	Nikos Nikoleris
2016-12-05	mem: Ensure InvalidateReq is considered isForward by MSHRs	Andreas Hansson
2016-12-05	mem: Make packet debug printing more uniform	Nikos Nikoleris
2016-12-05	mem: Service only the 1st FromCPU MSHR target on ReadRespWithInv	Nikos Nikoleris
2016-12-05	mem: Keep track of allocOnFill in the TargetList	Nikos Nikoleris
2016-12-05	mem: Add support for repopulating the flags of an MSHR TargetList	Nikos Nikoleris
2016-11-30	mem: Split the hit_latency into tag_latency and data_latency	Sophiane Senni
2016-08-15	mem: Print an MSHR without triggering any assertions	Nikos Nikoleris
2016-08-12	mem: Update mostly exclusive policy even further	Andreas Hansson
2016-08-12	mem: Update mostly exclusive cache policy to cover more cases	Andreas Hansson
2016-08-12	mem: Add a FromCache packet attribute	Andreas Hansson
2016-07-11	mem: Remove stale argument from a DPRINTF in the cache code	Nikos Nikoleris
2016-06-06	sim: Call regStats of base-class as well	Stephan Diestelhorst
2016-05-26	mem: Fix memory leak in handling of deferred snoops	Andreas Hansson
2016-05-26	mem: Do not set cacheResponding on MSHR snoop if not responding	Andreas Hansson
2016-05-26	mem: fix headers include order in the cache related classes	Nikos Nikoleris
2016-05-26	mem: remove redudant check whether the cache forwards snoops	Nikos Nikoleris
2016-05-26	mem: change NULL to nullptr in the cache related classes	Nikos Nikoleris
2016-05-26	mem: fix the line length in the cache related classes	Nikos Nikoleris
2016-04-21	mem: Include WriteLineReq in cache demand stats	Andreas Hansson
2016-04-21	mem: Remove unused cache stats	Andreas Hansson
2016-04-21	mem: Deallocate all write-queue entries when sent	Andreas Hansson
2016-04-21	mem: Align downstream cache packet creation in atomic and timing	Andreas Hansson
2016-04-07	mem: Add priority to QueuedPrefetcher	Rekai Gonzalez Alberquilla
2016-04-07	mem: Handful extra features for BasePrefetcher	Rekai Gonzalez Alberquilla
2015-05-27	mem: Add unused prefetch counter in caches	Rekai Gonzalez Alberquilla
2016-04-07	mem: Remove threadId from memory request class	Mitch Hayenga
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
2016-04-05	mem: Remove threadId from memory request class	Mitch Hayenga
2016-03-17	mem: Adjust cache queue reserve to more conservative values	Andreas Hansson
2016-03-17	mem: Create a separate class for the cache write buffer	Andreas Hansson
2015-08-10	mem, cpu: Add assertions to snoop invalidation logic	Stephan Diestelhorst
2016-02-24	mem: Ensure that InvalidateReq is not forwarded as ReadExReq	Andreas Hansson
2016-02-15	mem: Avoid using invalid iterator in cache lock list traversal	Andreas Hansson