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Age
Commit message (
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Author
2007-09-16
mem: clean up bus/cache DPRINTFs a bit
Steve Reinhardt
2007-08-30
params: Deprecate old-style constructors; update most SimObject constructors.
Miles Kaufmann
2007-08-26
Merge with head
Gabe Black
2007-08-12
MemorySystem: Fix the use of ?: to produce correct results.
Ali Saidi
2007-08-10
DMA: Add IOCache and fix bus bridge to optionally only send requests one
Ali Saidi
2007-08-03
cache: get rid of obsolete params from python.
Steve Reinhardt
2007-07-29
memory system: fix functional access bug.
Steve Reinhardt
2007-07-27
cache/memtest: fixes for functional accesses.
Steve Reinhardt
2007-07-27
cache: Get rid of unused variable.
Steve Reinhardt
2007-07-26
Merge python and x86 changes with cache branch
Nathan Binkert
2007-07-26
Have owner respond to UpgradeReq to avoid race.
Steve Reinhardt
2007-07-26
Add downward express snoops for invalidations.
Steve Reinhardt
2007-07-26
Continue snooping after a writeback is encountered.
Steve Reinhardt
2007-07-25
Can't block on memInhibit packets
Steve Reinhardt
2007-07-23
A couple more minor bug fixes for multilevel coherence.
Steve Reinhardt
2007-07-23
Major changes to how SimObjects are created and initialized. Almost all
Nathan Binkert
2007-07-22
Replace lowerMSHRPending flag with more robust scheme
Steve Reinhardt
2007-07-22
Replace DeferredSnoop flag with LowerMSHRPending flag.
Steve Reinhardt
2007-07-22
A few minor non-debug compilation issues.
Steve Reinhardt
2007-07-21
Deal with invalidations intersecting outstanding upgrades.
Steve Reinhardt
2007-07-21
Several more fixes for multi-level timing coherence.
Steve Reinhardt
2007-07-17
Forward cache-to-cache responses through other caches.
Steve Reinhardt
2007-07-17
Assert that an mshr has a target in getTarget().
Steve Reinhardt
2007-07-15
Fix up a bunch of multilevel coherence issues.
Steve Reinhardt
2007-07-14
Add CacheRepl trace flag and move a couple DPRINTFs to it.
Steve Reinhardt
2007-07-14
Move a couple of DPRINTFs from Cache to CachePort.
Steve Reinhardt
2007-07-14
Fix & tweak DPRINTFs for tracediff w/new cache code.
Steve Reinhardt
2007-07-03
Delete packets when we're done with them.
Steve Reinhardt
2007-07-02
Couple more minor bug fixes for FS timing mode.
Steve Reinhardt
2007-06-30
Get rid of remaining traces of obsolete CoherenceProtocol object.
Steve Reinhardt
2007-06-30
Factor out a little more common code.
Steve Reinhardt
2007-06-30
Fix up a few statistics problems.
Steve Reinhardt
2007-06-30
Get rid of Packet result field. Error responses are
Steve Reinhardt
2007-06-27
Get rid of coherence protocol object.
Steve Reinhardt
2007-06-26
Revamp replacement-of-upgrade handling.
Steve Reinhardt
2007-06-26
Handle deferred snoops better.
Steve Reinhardt
2007-06-26
cache_impl.hh:
Steve Reinhardt
2007-06-26
Handle replacement of block with pending upgrade.
Steve Reinhardt
2007-06-25
Couple minor bug fixes...
Steve Reinhardt
2007-06-25
Get rid of requestCauses. Use timestamped queue to make
Steve Reinhardt
2007-06-24
Better handling of deferred targets.
Steve Reinhardt
2007-06-22
Fixes to hitLatency, blocking, buffer allocation.
Steve Reinhardt
2007-06-21
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2007-06-21
Getting closer...
Steve Reinhardt
2007-06-20
Make sure all parameters have default values if they're
Nathan Binkert
2007-06-17
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2007-06-17
More major reorg of cache. Seems to work for atomic mode now,
Steve Reinhardt
2007-06-09
More realistic parameters
Nathan Binkert
2007-05-27
Merge vm1.(none):/home/stever/bk/newmem-head
Steve Reinhardt
2007-05-27
Move SimObject python files alongside the C++ and fix
Nathan Binkert
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