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path: root/src/mem/cache
AgeCommit message (Expand)Author
2016-12-05mem: Service only the 1st FromCPU MSHR target on ReadRespWithInvNikos Nikoleris
2016-12-05mem: Keep track of allocOnFill in the TargetListNikos Nikoleris
2016-12-05mem: Add support for repopulating the flags of an MSHR TargetListNikos Nikoleris
2016-11-30mem: Split the hit_latency into tag_latency and data_latencySophiane Senni
2016-08-15mem: Print an MSHR without triggering any assertionsNikos Nikoleris
2016-08-12mem: Update mostly exclusive policy even furtherAndreas Hansson
2016-08-12mem: Update mostly exclusive cache policy to cover more casesAndreas Hansson
2016-08-12mem: Add a FromCache packet attributeAndreas Hansson
2016-07-11mem: Remove stale argument from a DPRINTF in the cache codeNikos Nikoleris
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-05-26mem: Fix memory leak in handling of deferred snoopsAndreas Hansson
2016-05-26mem: Do not set cacheResponding on MSHR snoop if not respondingAndreas Hansson
2016-05-26mem: fix headers include order in the cache related classesNikos Nikoleris
2016-05-26mem: remove redudant check whether the cache forwards snoopsNikos Nikoleris
2016-05-26mem: change NULL to nullptr in the cache related classesNikos Nikoleris
2016-05-26mem: fix the line length in the cache related classesNikos Nikoleris
2016-04-21mem: Include WriteLineReq in cache demand statsAndreas Hansson
2016-04-21mem: Remove unused cache statsAndreas Hansson
2016-04-21mem: Deallocate all write-queue entries when sentAndreas Hansson
2016-04-21mem: Align downstream cache packet creation in atomic and timingAndreas Hansson
2016-04-07mem: Add priority to QueuedPrefetcherRekai Gonzalez Alberquilla
2016-04-07mem: Handful extra features for BasePrefetcherRekai Gonzalez Alberquilla
2015-05-27mem: Add unused prefetch counter in cachesRekai Gonzalez Alberquilla
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2016-03-17mem: Adjust cache queue reserve to more conservative valuesAndreas Hansson
2016-03-17mem: Create a separate class for the cache write bufferAndreas Hansson
2015-08-10mem, cpu: Add assertions to snoop invalidation logicStephan Diestelhorst
2016-02-24mem: Ensure that InvalidateReq is not forwarded as ReadExReqAndreas Hansson
2016-02-15mem: Avoid using invalid iterator in cache lock list traversalAndreas Hansson
2016-02-10mem: Be less conservative in clearing load locks in the cacheAndreas Hansson
2016-02-10mem: Move the point of coherency to the coherent crossbarAndreas Hansson
2016-02-10mem: Align cache behaviour in atomic when upstream is respondingAndreas Hansson
2016-02-10mem: Align how snoops are handled when hitting writebacksAndreas Hansson
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2015-12-31mem: add CacheVerbose debug flag, filter noisy DPRINTFsSteve Reinhardt
2015-12-31mem: Do not allocate space for packet data if not neededAndreas Hansson
2015-12-31mem: Do not alter cache block state on uncacheable snoopsAndreas Hansson
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-12-28mem: Explicitly check MSHR snoops for cases not dealt withAndreas Hansson
2015-12-28mem: Remove unused cache squash functionalityAndreas Hansson
2015-12-28mem: Avoid unecessary checks when creating HardPFReq in cacheAndreas Hansson
2015-12-28mem: Do not use sender state to track forwarded snoops in cacheAndreas Hansson
2015-12-28mem: Fix cache sender state handling and add clarificationAndreas Hansson
2015-12-17mem: Fix memory allocation bug in deferred snoop handlingAndreas Hansson
2015-11-15arm: Add missing explicit overrides for classic cachesAndreas Sandberg
2015-11-06mem: Add an option to perform clean writebacks from cachesAndreas Hansson
2015-11-06mem: Add cache clusivityAndreas Hansson
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