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path: root/src/mem/cache
AgeCommit message (Expand)Author
2008-11-04decouple eviction from insertion in the cache.Lisa Hsu
2008-11-04Change the findBlock(addr, lat) to accessBlock, which I think has better conn...Lisa Hsu
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-10-23s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos inLisa Hsu
2008-10-23probe function no longer used anywhere.Lisa Hsu
2008-10-23remove the totally obsolete split cacheLisa Hsu
2008-10-14This function declaration isn't used anywhere.Lisa Hsu
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul...Ali Saidi
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
2008-06-13Get rid of bogus cache assertion.Steve Reinhardt
2008-05-15Make sure that output files are always checked success before they're used.Ali Saidi
2008-03-25Fix handling of writeback-induced writebacks in atomic mode.Steve Reinhardt
2008-03-24Don't FastAlloc MSHRs since we don't allocate them on the fly.Steve Reinhardt
2008-03-22Fix cache problem with writes to tempBlockSteve Reinhardt
2008-03-17Fix a few Packet memory leaks.Steve Reinhardt
2008-03-15Fix subtle cache bug where read could return stale dataSteve Reinhardt
2008-02-26Revamp cache timing access mshr check to make stats sane again.Steve Reinhardt
2008-02-26Cache: better comments particularly regarding writeback situation.Steve Reinhardt
2008-02-16Make L2+ caches allocate new block for writeback missesSteve Reinhardt
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
2008-01-06Temporary fix for ll/sc bug see flyspray task for more info:Geoffrey Blake
2008-01-02Add ReadRespWithInvalidate to handle multi-level coherence situationSteve Reinhardt
2008-01-02Mark cache-to-cache MSHRs as downstreamPending when necessary.Steve Reinhardt
2008-01-02Don't DPRINTF in the middle of a PrintReq.Steve Reinhardt
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
2008-01-02Fix formatting and comments in cache_impl.hhSteve Reinhardt
2007-11-16Tweak check for writable block fill.Steve Reinhardt
2007-11-16Fix bug on exclusive response to ReadReq with pending WriteReq.Steve Reinhardt
2007-11-04Cache: Fix for OS X 10.5 compiling.Ali Saidi
2007-10-31Merge in bus DPRINTF changes.Steve Reinhardt
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one f...Ali Saidi
2007-09-16mem: clean up bus/cache DPRINTFs a bitSteve Reinhardt
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
2007-08-26Merge with headGabe Black
2007-08-12MemorySystem: Fix the use of ?: to produce correct results.Ali Saidi
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
2007-08-03cache: get rid of obsolete params from python.Steve Reinhardt
2007-07-29memory system: fix functional access bug.Steve Reinhardt
2007-07-27cache/memtest: fixes for functional accesses.Steve Reinhardt
2007-07-27cache: Get rid of unused variable.Steve Reinhardt
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-26Have owner respond to UpgradeReq to avoid race.Steve Reinhardt
2007-07-26Add downward express snoops for invalidations.Steve Reinhardt
2007-07-26Continue snooping after a writeback is encountered.Steve Reinhardt
2007-07-25Can't block on memInhibit packetsSteve Reinhardt
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