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path: root/src/mem/cache
AgeCommit message (Expand)Author
2014-09-27misc: Fix a bunch of minor issues identified by static analysisAndreas Hansson
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20mem: Remove the GHB prefetcher from the source treeMitch Hayenga
2014-09-19misc: Remove assertions ensuring unsigned values >= 0Andreas Hansson
2014-09-19mem: Add checks to sendTimingReq in cacheAndreas Hansson
2014-09-09misc: Fix a number of unitialised variables and membersAndreas Hansson
2014-06-27mem: write streaming support via WriteInvalidate promotionCurtis Dunham
2014-09-03mem: Fix a bug in the cache port flow controlAndreas Hansson
2014-05-13cpu, mem: Make software prefetches non-blockingCurtis Dunham
2014-09-03cache: Fix handling of LL/SC requests under contentionGeoffrey Blake
2014-09-03arch: Cleanup unused ISA traits constantsAndreas Hansson
2014-08-13mem: Properly set cache block status fields on writebacksMitch Hayenga
2014-07-28mem: refactor LRU cache tags and add random replacement tagsAnthony Gutierrez
2014-05-09mem: Squash prefetch requests from downstream cachesMitch Hayenga
2014-04-01mem: Don't print out the data of a cache blockMitch Hayenga
2014-03-07mem: Fix incorrect assert failure in the CachePrakash Ramrakhyani
2014-02-18mem: Filter cache snoops based on address rangesAndreas Hansson
2014-01-29mem: Add additional tolerance to stride prefetcherMitch Hayenga
2014-01-29mem: Allowed tagged instruction prefetching in stride prefetcherMitch Hayenga
2014-01-29mem: prefetcher: add options, support for unaligned addressesMitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-28mem: Remove redundant findVictim() input argumentAmin Farmahini
2014-01-24mem: Add support for a security bit in the memory systemGiacomo Gabrielli
2014-01-24Cache: Collect very basic stats on tag and data accessesTimothy M. Jones
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-07-18mem: Add cache class destructor to avoid memory leaksXiangyu Dong
2013-06-27mem: Reorganize cache tags and make them a SimObjectPrakash Ramrakhyani
2013-06-27mem: Remove the cache builderAndreas Hansson
2013-06-27mem: Align cache timing to clock edgesAndreas Hansson
2013-06-27mem: Cycles converted to Ticks in atomic cache accessesAndreas Hansson
2013-06-27mem: Remove a redundant heap allocation for a snoop packetAndreas Hansson
2013-05-30mem: Spring cleaning of MSHR and MSHRQueueAndreas Hansson
2013-05-30mem: Fix MSHR print formatAndreas Hansson
2013-04-22mem: Adding verbose debug output in the memory systemUri Wiener
2013-03-27mem: Fix cache latency bugMitch Hayenga
2013-03-26mem: Cancel cache retry event when blocking portRene de Jong
2013-02-19mem: Fix sender state bug and delay poppingAndreas Hansson
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2013-02-19mem: Change accessor function names to match the port interfaceAndreas Hansson
2013-02-19mem: Make packet bus-related time accounting relativeAndreas Hansson
2013-02-19mem: Add deferred packet class to prefetcherAndreas Hansson
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2013-02-19mem: Fix SenderState related cache deadlockSascha Bischoff
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
2013-02-15mem: Tighten up cache constness and scopingAndreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
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