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AgeCommit message (Collapse)Author
2010-11-19SCons: Support building without an ISAAli Saidi
2010-10-18cache: minor SC assertion fixSteve Reinhardt
Thanks to Joe Gross for finding/testing this.
2010-10-13Mem: Change the CLREX flag to CLEAR_LL.Gabe Black
CLREX is the name of an ARM instruction, not a name for this generic flag.
2010-09-21cache: improve coherence handling of writebacksSteve Reinhardt
If we write back an exclusive copy, we now mark it as such, so the cache receiving the writeback can mark its copy as exclusive. This avoids some unnecessary upgrade requests when a cache later tries to re-acquire exclusive access to the block.
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2010-09-09cache: fail SC when invalidated while waiting for busSteve Reinhardt
Corrects an oversight in cset f97b62be544f. The fix there only failed queued SCUpgradeReq packets that encountered an invalidation, which meant that the upgrade had to reach the L2 cache. To handle pending requests in the L1 we must similarly fail StoreCondReq packets too.
2010-09-09mem: fix functional accesses to deal with coherence changeSteve Reinhardt
We can't just obliviously return the first valid cache block we find any more... see comments for details.
2010-09-09cache: coherence protocol enhancements & bug fixesSteve Reinhardt
Allow lower-level caches (e.g., L2 or L3) to pass exclusive copies to higher levels (e.g., L1). This eliminates a lot of unnecessary upgrade transactions on read-write sequences to non-shared data. Also some cleanup of MSHR coherence handling and multiple bug fixes.
2010-08-26mem: fix m5.fast compile bug in previous csetSteve Reinhardt
2010-08-25cache: fix a bug in atomic multilevel snoopsSteve Reinhardt
2010-08-25mem: fix dumb typo in copyrightsSteve Reinhardt
2010-08-23MEM: Make CLREX a first class request operation and clear locks in caches ↵Gene Wu
when it in received
2010-08-23ARM: Make sure that software prefetch instructions can't change the state of ↵Gene Wu
the TLB
2010-08-23Compiler: Fixes for GCC 4.5.Ali Saidi
2010-07-22Port: Only indicate that a SimpleTimingPort is drained if its send event isTimothy M. Jones
not scheduled, as well as the transmit list being empty.
2010-07-08cache: fix bug in SC upgrade handlingSteve Reinhardt
This bug was introduced with the recent rework of SC failure handling in cset f97b62be544f.
2010-06-22cache: fix longstanding prefetcher bugSteve Reinhardt
Thanks to Joe Gross for pointing this out (again?). Apologies to anyone who pointed it out earlier and we didn't listen.
2010-06-16cache: fail store conditionals when upgrade loses raceSteve Reinhardt
Requires new "SCUpgradeReq" message that marks upgrades for store conditionals, so downstream caches can fail these when they run into invalidations. See http://www.m5sim.org/flyspray/task/197
2010-06-16cache: fix dirty bit settingSteve Reinhardt
Only set the dirty bit when we actually write to a block (not if we thought we might but didn't, as in a failed SC or CAS). This requires makeing sure the dirty bit stays set when we get an exclusive (writable) copy in a cache-to-cache transfer from another owner, which n turn requires copying the mem-inhibit flag from timing-mode requests to their associated responses.
2010-06-15stats: only consider a formula initialized if there is a formulaNathan Binkert
2010-02-24cache stats: account for writebacks and/or device occupancy in the cache.Lisa Hsu
Plus, a minor bugfix that neglects to update blk->contextSrc in certain cases on a cache insert.
2010-02-23cache: Make caches sharing aware and add occupancy stats.Lisa Hsu
On the config end, if a shared L2 is created for the system, it is parameterized to have n sharers as defined by option.num_cpus. In addition to making the cache sharing aware so that discriminating tag policies can make use of context_ids to make decisions, I added an occupancy AverageStat and an occ % stat to each cache so that you could know which contexts are occupying how much cache on average, both in terms of blocks and percentage. Note that since devices have context_id -1, having an array of occ stats that correspond to each context_id will break here, so in FS mode I add an extra bucket for device blocks. This bucket is explicitly not added in SE mode in order to not only avoid ugliness in the stats.txt file, but to avoid broken stats (some formulas break when a bucket is 0).
2010-02-23cache: pull CacheSet out of LRU so that other tags can use associative sets.Lisa Hsu
2010-01-12cache: make tags->insertBlock() and tags->accessBlock() context aware so ↵Lisa Hsu
that the cache can make context-specific decisions within their various tag policy implementations.
2009-09-26Minor cleanup: Use the blockAlign() method where it applies in the cache.Steve Reinhardt
2009-09-26Force prefetches to check cache and MSHRs immediately prior to issue.Steve Reinhardt
This prevents redundant prefetches from being issued, solving the occasional 'needsExclusive && !blk->isWritable()' assertion failure in cache_impl.hh that several people have run into. Eliminates "prefetch_cache_check_push" flag, neither setting of which really solved the problem.
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-08-01Fix setting of INST_FETCH flag for O3 CPU.Steve Reinhardt
It's still broken in inorder. Also enhance DPRINTFs in cache and physical memory so we can see more easily whether it's getting set or not.
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17includes: use base/types.hh not inttypes.h or stdint.hNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
--HG-- rename : src/sim/host.hh => src/base/types.hh
2008-07-16mem: use single BadAddr responder per system.Steve Reinhardt
Previously there was one per bus, which caused some coherence problems when more than one decided to respond. Now there is just one on the main memory bus. The default bus responder on all other buses is now the downstream cache's cpu_side port. Caches no longer need to do address range filtering; instead, we just have a simple flag to prevent snoops from propagating to the I/O bus.
2009-04-20request: rename INST_READ to INST_FETCH.Steve Reinhardt
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-03-11cache: set dirty bit on swaps (oops!)Steve Reinhardt
2009-03-10prefetch: don't panic on requests w/o contextID (e.g., writebacks).Steve Reinhardt
2009-03-05stats: Fix all stats usages to deal with template fixesNathan Binkert
2009-02-16Fixes to get prefetching working again.Steve Reinhardt
Apparently we broke it with the cache rewrite and never noticed. Thanks to Bao Yungang <baoyungang@gmail.com> for a significant part of these changes (and for inspiring me to work on the rest). Some other overdue cleanup on the prefetch code too.
2008-11-14Cache: get rid of obsolete Tag methods.Steve Reinhardt
I think readData() and writeData() were used for Erik's compression work, but that code is gone, these aren't called anymore, and they don't even really do what their names imply.
2008-11-10Cache: Refactor packet forwarding a bit.Steve Reinhardt
Makes adding write-through operations easier.
2008-11-04decouple eviction from insertion in the cache.Lisa Hsu
2008-11-04Change the findBlock(addr, lat) to accessBlock, which I think has better ↵Lisa Hsu
connotations for what is really happening and how it should be used.
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
redundancies with threadId() as their replacement.
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.
2008-10-23s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos inLisa Hsu
comments.
2008-10-23probe function no longer used anywhere.Lisa Hsu
2008-10-23remove the totally obsolete split cacheLisa Hsu