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path: root/src/mem/cache
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2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5.
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers ↵Ali Saidi
should configure their editors to not insert tabs
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
Force all non-default ports to provide a name and an owner in the constructor.
2008-06-13Get rid of bogus cache assertion.Steve Reinhardt
I was asserting that the only reason you would defer targets is if a write came in while you had an outstanding read miss, but there's another case where you could get a read access after you've snooped an invalidation and buffered it because it applies to a prior outstanding miss.
2008-05-15Make sure that output files are always checked success before they're used.Ali Saidi
Make OutputDirectory::resolve() private and change the functions using resolve() to instead use create(). --HG-- extra : convert_revision : 36d4be629764d0c4c708cec8aa712cd15f966453
2008-03-25Fix handling of writeback-induced writebacks in atomic mode.Steve Reinhardt
--HG-- extra : convert_revision : 4fa64f8a929f1aa36a9d5a71b8d1816b497aca4c
2008-03-24Don't FastAlloc MSHRs since we don't allocate them on the fly.Steve Reinhardt
--HG-- extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
2008-03-22Fix cache problem with writes to tempBlockSteve Reinhardt
getting wrong writeback address. --HG-- extra : convert_revision : 023dfb69c227c13a69bfe2744c6af75a45828b0b
2008-03-17Fix a few Packet memory leaks.Steve Reinhardt
--HG-- extra : convert_revision : 00db19f0698c0786f0dff561eea9217860a5a05a
2008-03-15Fix subtle cache bug where read could return stale dataSteve Reinhardt
if a prior write miss arrived while an even earlier read miss was still outstanding. --HG-- extra : convert_revision : 4924e145829b2ecf4610b88d33f4773510c6801a
2008-02-26Revamp cache timing access mshr check to make stats sane again.Steve Reinhardt
--HG-- extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea
2008-02-26Cache: better comments particularly regarding writeback situation.Steve Reinhardt
--HG-- extra : convert_revision : 59ff9ee63ee0fec5a7dfc27b485b737455ccf362
2008-02-16Make L2+ caches allocate new block for writeback missesSteve Reinhardt
instead of forwarding down the line. --HG-- extra : convert_revision : b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
--HG-- extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
2008-02-10Rename cache files for brevity and consistency with rest of tree.Steve Reinhardt
--HG-- rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh extra : convert_revision : ff7a35cc155a8d80317563c45cebe405984eac62
2008-01-06Temporary fix for ll/sc bug see flyspray task for more info:Geoffrey Blake
http://www.m5sim.org/flyspray/task/197 Signed-off by: Ali Saidi <saidi@eecs.umich.edu> --HG-- extra : convert_revision : cdeece7e3163de9abf2c6c7435f1bc93570fab81
2008-01-02Add ReadRespWithInvalidate to handle multi-level coherence situationSteve Reinhardt
where we defer a response to a read from a far-away cache A, then later defer a ReadExcl from a cache B on the same bus as us. We'll assert MemInhibit in both cases, but in the latter case MemInhibit will keep the invalidation from reaching cache A. This special response tells cache A that it gets the block to satisfy its read, but must immediately invalidate it. --HG-- extra : convert_revision : f85c8b47bb30232da37ac861b50a6539dc81161b
2008-01-02Mark cache-to-cache MSHRs as downstreamPending when necessary.Steve Reinhardt
Don't mark upstream MSHR as pending if downstream MSHR is already in service. --HG-- extra : convert_revision : e1c135ff00217291db58ce8a06ccde34c403d37f
2008-01-02Don't DPRINTF in the middle of a PrintReq.Steve Reinhardt
--HG-- extra : convert_revision : 6358c014d14a19a34111c39827b05987507544bb
2008-01-02Additional comments and helper functions for PrintReq.Steve Reinhardt
--HG-- extra : convert_revision : 7eadf9b7db8c0289480f771271b6efe2400006d4
2008-01-02Add functional PrintReq command for memory-system debugging.Steve Reinhardt
--HG-- extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
2008-01-02Fix formatting and comments in cache_impl.hhSteve Reinhardt
--HG-- extra : convert_revision : 26d71cca5420ad03e16bf174e15dabe7f902da41
2007-11-16Tweak check for writable block fill.Steve Reinhardt
--HG-- extra : convert_revision : c04281bcfc4cd23c7613aeccb21dc74452bcc951
2007-11-16Fix bug on exclusive response to ReadReq with pending WriteReq.Steve Reinhardt
--HG-- extra : convert_revision : 5429cd7ca84cf6348813a4607fa16f76aa5df7e0
2007-11-04Cache: Fix for OS X 10.5 compiling.Ali Saidi
--HG-- extra : convert_revision : ba3c33ed524367280eefc096177d767168ac2cf6
2007-10-31Merge in bus DPRINTF changes.Steve Reinhardt
--HG-- extra : convert_revision : 3bbd7c0745b31bb2a628b604ab1627cd9c61643c
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one ↵Ali Saidi
file with them all. --HG-- extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-09-16mem: clean up bus/cache DPRINTFs a bitSteve Reinhardt
Not so much noise on failed sends, and more complete info when grepping a trace using an address. --HG-- extra : convert_revision : 05a8261c9452072ca08b906200c6322b33e2b9f1
2007-08-30params: Deprecate old-style constructors; update most SimObject constructors.Miles Kaufmann
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name)) --HG-- extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
2007-08-26Merge with headGabe Black
--HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
2007-08-12MemorySystem: Fix the use of ?: to produce correct results.Ali Saidi
--HG-- extra : convert_revision : 31aad7170b35556a4c984f4ebc013137d55d85eb
2007-08-10DMA: Add IOCache and fix bus bridge to optionally only send requests oneAli Saidi
way so a cache can handle partial block requests for i/o devices. --HG-- extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
2007-08-03cache: get rid of obsolete params from python.Steve Reinhardt
--HG-- extra : convert_revision : cd40e0ef938ef6da1cccedf7be01c3ac5b4883fb
2007-07-29memory system: fix functional access bug.Steve Reinhardt
Make sure not to keep processing functional accesses after they've been responded to. Also use checkFunctional() return value instead of checking packet command field where possible, mostly just for consistency. --HG-- extra : convert_revision : 29fc76bc18731bd93a4ed05a281297827028ef75
2007-07-27cache/memtest: fixes for functional accesses.Steve Reinhardt
--HG-- extra : convert_revision : 688ba4d882cad2c96cf44c9e46999f74266e02ee
2007-07-27cache: Get rid of unused variable.Steve Reinhardt
--HG-- extra : convert_revision : 394adc12fbd7ea10280a1b8d6bc3cb15ee019f27
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
--HG-- extra : convert_revision : e06a950964286604274fba81dcca362d75847233
2007-07-26Have owner respond to UpgradeReq to avoid race.Steve Reinhardt
--HG-- extra : convert_revision : 30916fca6978c73d8a14558f2d7288c1eab54ad4
2007-07-26Add downward express snoops for invalidations.Steve Reinhardt
--HG-- extra : convert_revision : 4916fa9721d727d8416ad8c07df3a8171d02b2b4
2007-07-26Continue snooping after a writeback is encountered.Steve Reinhardt
--HG-- extra : convert_revision : 8411338a6c0fdd7072dd32bdffacdace62d5de90
2007-07-25Can't block on memInhibit packetsSteve Reinhardt
(now that bus no longer filters them for us). --HG-- extra : convert_revision : 34e7eaf5ee1e739f5557a2d417e569ed2ceb14b3
2007-07-23A couple more minor bug fixes for multilevel coherence.Steve Reinhardt
--HG-- extra : convert_revision : 370f9e34911157765be6fd49e826fa1af589b466
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-22Replace lowerMSHRPending flag with more robust schemeSteve Reinhardt
based on following Packet senderState links. --HG-- extra : convert_revision : 9027d59bd7242aa0e4275bf94d8b1fb27bd59d79
2007-07-22Replace DeferredSnoop flag with LowerMSHRPending flag.Steve Reinhardt
Turns out DeferredSnoop isn't quite the right bit of info we needed... see new comment in cache_impl.hh. --HG-- extra : convert_revision : a38de8c1677a37acafb743b7074ef88b21d3b7be
2007-07-22A few minor non-debug compilation issues.Steve Reinhardt
--HG-- extra : convert_revision : d59a5cad6187a2229dddd1a48282ebd2923d1d8d
2007-07-21Deal with invalidations intersecting outstanding upgrades.Steve Reinhardt
If the invalidation beats the upgrade at a lower level then the upgrade must be converted to a read exclusive "in the field". Restructure target list & deferred target list to factor out some common code. --HG-- extra : convert_revision : 7bab4482dd6c48efdb619610f0d3778c60ff777a
2007-07-21Several more fixes for multi-level timing coherence.Steve Reinhardt
- Add "deferred snoop" flag to Packet so upper-level caches can distinguish whether lower-level cache request was in-service or not at the time of the original snoop. - Revamp response handling to properly handle deferred snoops on non-cache-fill requests (i.e. upgrades). - Make sure forwarded writebacks are kept in write buffer at lower-level caches so they get snooped properly. --HG-- extra : convert_revision : 17f8a3772a1ae31a16991a53f8225ddf54d31fc9
2007-07-17Forward cache-to-cache responses through other caches.Steve Reinhardt
--HG-- extra : convert_revision : 5b6a02255bccd98b00949703cf4ba4b221553cea
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