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path: root/src/mem/cache
AgeCommit message (Expand)Author
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-09-04arch: Resurrect the NOISA build target and rename it NULLAndreas Hansson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-07-18mem: Add cache class destructor to avoid memory leaksXiangyu Dong
2013-06-27mem: Reorganize cache tags and make them a SimObjectPrakash Ramrakhyani
2013-06-27mem: Remove the cache builderAndreas Hansson
2013-06-27mem: Align cache timing to clock edgesAndreas Hansson
2013-06-27mem: Cycles converted to Ticks in atomic cache accessesAndreas Hansson
2013-06-27mem: Remove a redundant heap allocation for a snoop packetAndreas Hansson
2013-05-30mem: Spring cleaning of MSHR and MSHRQueueAndreas Hansson
2013-05-30mem: Fix MSHR print formatAndreas Hansson
2013-04-22mem: Adding verbose debug output in the memory systemUri Wiener
2013-03-27mem: Fix cache latency bugMitch Hayenga
2013-03-26mem: Cancel cache retry event when blocking portRene de Jong
2013-02-19mem: Fix sender state bug and delay poppingAndreas Hansson
2013-02-19scons: Fix up numerous warnings about name shadowingAndreas Hansson
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2013-02-19mem: Change accessor function names to match the port interfaceAndreas Hansson
2013-02-19mem: Make packet bus-related time accounting relativeAndreas Hansson
2013-02-19mem: Add deferred packet class to prefetcherAndreas Hansson
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2013-02-19mem: Fix SenderState related cache deadlockSascha Bischoff
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
2013-02-15mem: Tighten up cache constness and scopingAndreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-01-28cache: remove drainManager because it's not usedAnthony Gutierrez
2013-01-08mem: Make LL/SC locks fine grainedMitch Hayenga
2013-01-07mem: Fix guest corruption when caches handle uncacheable accessesAndreas Sandberg
2013-01-07mem: Remove the IIC replacement policyAndreas Sandberg
2013-01-07sim: Fatal if a clocked object is set to have a clock of 0Andreas Hansson
2013-01-07cache: add note about where conflicts are handledAli Saidi
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25MEM: Put memory system document into doxygenDjordje Kovacevic
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-11clang: Fix issues identified by the clang static analyzerAndreas Hansson
2012-09-11Cache: Split invalidateBlk up to seperate block vs. tagsLena Olson
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-07-27cache: don't allow dirty data in the i-cacheAnthony Gutierrez
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
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