gem5 - gem5

Age	Commit message (Expand)	Author
2013-01-07	mem: Remove the IIC replacement policy	Andreas Sandberg
2013-01-07	sim: Fatal if a clocked object is set to have a clock of 0	Andreas Hansson
2013-01-07	cache: add note about where conflicts are handled	Ali Saidi
2012-11-02	mem: Add support for writing back and flushing caches	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-09-25	MEM: Put memory system document into doxygen	Djordje Kovacevic
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-11	clang: Fix issues identified by the clang static analyzer	Andreas Hansson
2012-09-11	Cache: Split invalidateBlk up to seperate block vs. tags	Lena Olson
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-22	Port: Extend the QueuedPort interface and use where appropriate	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-07-27	cache: don't allow dirty data in the i-cache	Anthony Gutierrez
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-07-09	Port: Add isSnooping to slave port (asking master port)	Andreas Hansson
2012-07-09	Port: Move retry from port base class to Master/SlavePort	Andreas Hansson
2012-07-09	Fix: Address a few benign memory leaks	Andreas Hansson
2012-06-29	Cache: Fix the LRU policy for classic memory hierarchy	Lena Olson
2012-06-29	Mem: fix master id assertion in cache_impl.hh	Dam Sunwoo
2012-06-29	Cache: Only invalidate a line in the cache when an uncacheable write is seen.	Ali Saidi
2012-06-07	mem: Delay deleting of incoming packets by one call.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-05-30	Bus: Turn the PortId into a transport function parameter	Andreas Hansson
2012-05-30	Packet: Unify the use of PortID in packet and port	Andreas Hansson
2012-05-24	Cache: Remove dangling doWriteback declaration	Andreas Hansson
2012-05-10	Cache: restructure code that actually isn't a loop	Ali Saidi
2012-05-10	gem5: fix some iterator use and erase bugs	Ali Saidi
2012-05-10	gem5: Fix a number of incorrect case statements	Ali Saidi
2012-05-10	Cache: Panic if you attempt to create a checkpoint with a cache in the system	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-01	Cache: Fix an issue with LRU when bonus block is used to complete transaction.	Ali Saidi
2012-02-24	MEM: Simplify cache ports preparing for master/slave split	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: fix cache stats to use request ids correctly	Dam Sunwoo
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black