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2007-02-12rename store conditional stuff as extra data so it can be used for ↵Ali Saidi
conditional swaps as well Add support for a twin 64 bit int load Add Memory barrier and write barrier flags as appropriate Make atomic memory ops atomic src/arch/alpha/isa/mem.isa: src/arch/alpha/locked_mem.hh: src/cpu/base_dyn_inst.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: rename store conditional stuff as extra data so it can be used for conditional swaps as well src/arch/alpha/types.hh: src/arch/mips/types.hh: src/arch/sparc/types.hh: add a largest read data type for statically allocating read buffers in atomic simple cpu src/arch/isa_parser.py: Add support for a twin 64 bit int load src/arch/sparc/isa/decoder.isa: Make atomic memory ops atomic Add Memory barrier and write barrier flags as appropriate src/arch/sparc/isa/formats/mem/basicmem.isa: add post access code block and define a twinload format for twin loads src/arch/sparc/isa/formats/mem/blockmem.isa: remove old microcoded twin load coad src/arch/sparc/isa/formats/mem/mem.isa: swap.isa replaces the code in loadstore.isa src/arch/sparc/isa/formats/mem/util.isa: add a post access code block src/arch/sparc/isa/includes.isa: need bigint.hh for Twin64_t src/arch/sparc/isa/operands.isa: add a twin 64 int type src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: add support for twinloads add support for swap and conditional swap instructions rename store conditional stuff as extra data so it can be used for conditional swaps as well src/mem/packet.cc: src/mem/packet.hh: Add support for atomic swap memory commands src/mem/packet_access.hh: Add endian conversion function for Twin64_t type src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: Add support for atomic swap memory commands Rename sc code to extradata --HG-- extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
2007-02-07Merge zizzer.eecs.umich.edu:/bk/newmemSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-head --HG-- extra : convert_revision : c2350e01a052114a264f26551b13fca03a835c61
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
Created MemCmd class to wrap enum and provide handy methods to check attributes, convert to string/int, etc. --HG-- extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-02-06Minor DPRINTF fixes.Steve Reinhardt
--HG-- extra : convert_revision : 41956c9a480163ecac7807982215027e8ff1a4a9
2007-02-06Fix for LL/SC that Ron sent me.Kevin Lim
--HG-- extra : convert_revision : b3510a23d8a9eb466939f38491a109c3a65a7363
2007-01-26make our code a little more standards compliantAli Saidi
pretty close to compiling w/ suns compiler briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc --HG-- extra : convert_revision : ef8a1f1064e43b6c39838a85c01aee4f795497bd
2006-12-18Streamline Cache/Tags interface: get rid of redundant functions,Steve Reinhardt
don't regenerate address from block in cache so that tags can turn around and use address to look up block again. --HG-- extra : convert_revision : 171018aa6e331d98399c4e5ef24e173c95eaca28
2006-12-18No need to template prefetcher on cache TagStore type.Steve Reinhardt
--HG-- rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc extra : convert_revision : 56c0b51e424a3a6590332dba4866e69a1ad19598
2006-12-18Get rid of generic CacheTags object (fold back into Cache).Steve Reinhardt
--HG-- extra : convert_revision : 8769bd8cc358ab3cbbdbbcd909b2e0f1515e09da
2006-12-13Split CachePort class into CpuSidePort and MemSidePortSteve Reinhardt
and push those into derived Cache template class to eliminate a few layers of virtual functions and conditionals ("if (isCpuSide) { ... }" etc.). --HG-- extra : convert_revision : cb1b88246c95b36aa0cf26d534127d3714ddb774
2006-12-05Don't compress data on writebacks unless it's actually necessary.Steve Reinhardt
--HG-- extra : convert_revision : 7a068e28f9ea2f6aab57be7133b47bda72d10302
2006-12-04Turn cache MissQueue/BlockingBuffer into virtual objectSteve Reinhardt
instead of template parameter. --HG-- extra : convert_revision : fce0fbd041149b9c781eb23f480ba84fddbfd4a0
2006-12-02Make cache compression policy a runtime virtual thingSteve Reinhardt
instead of a template policy. --HG-- extra : convert_revision : 6a4ac7a189a950390a973fdfce94f56190de92db
2006-11-28Remove assertion. It's not needed and messes up writebacks when a 2 level ↵Kevin Lim
cache is used in a uniprocessor setting. --HG-- extra : convert_revision : 020a9799cd7177fdb85a767701d6fcb8cf018827
2006-11-22Do a functional access to levels above on a read as a temporary solution for ↵Ron Dreslinski
L2's in FS Fix a small writeback bug when missing in the L2 in atomic mode src/mem/bus.cc: Fix a comment to make sense src/mem/cache/cache_impl.hh: Do a functional access to levels above on a read as a temporary solution for L2's in FS Also fix a small writeback miss in L2 issue src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Do a functional access to levels above on a read as a temporary solution for L2's in FS tests/quick/00.hello/ref/alpha/linux/o3-timing/m5stats.txt: tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt: tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt: Update ref's for writeback changes --HG-- extra : convert_revision : 937febd577b16b7fd97a5a68acaf53541828a251
2006-11-13Fix a bug to handle the fact that a CPU can send Functional accesses while a ↵Ron Dreslinski
sendTiming has not returned in the call stack. src/mem/cache/base_cache.cc: Sometimes a functional access comes while waiting on a outstanding packet being sent. This could be because Timing CPU does some post processing on the recvTiming which send functional access. Either the CPU should leave the pkt/req around (so They can be referenced in the mem system). Or the mem system should remove them from outstanding lists and reinsert them if they fail in the sendTiming. I did the later, eventually we should consider doing the former if that is the correct behavior. --HG-- extra : convert_revision : be41e0d2632369dca9d7c15e96e5576d7583fe6a
2006-11-13If we didn't satisfy all targets, reset the packet we are requesting with.Ron Dreslinski
--HG-- extra : convert_revision : 736372131b046eccf3520292fb3c086dc568d918
2006-11-13Since cpus now send out snoop ranges, remove it from the cache.Ron Dreslinski
--HG-- extra : convert_revision : 82882eb131aa66eba9f281b64db21d5cbfefb1b9
2006-11-12Handle packets being deleted by lower level properly.Ron Dreslinski
Fixes for Mem Leak associated with Writebacks. src/mem/cache/miss/mshr_queue.cc: Fixes for Mem Leak associated with Writebacks. (Double Delete removed) --HG-- extra : convert_revision : 7a52ddd57da35995896f2c4438a58aa53f762416
2006-11-12Don't insert reponses into the list more than onceRon Dreslinski
If you get inserted in the front, reschedule the event --HG-- extra : convert_revision : eccbacf5ec85600e5b68eb554fee2c0e2b65e965
2006-11-12Move code before a early return to make sure it is executed on all pathsRon Dreslinski
--HG-- extra : convert_revision : cfdd5b6911422fbb733677c43d027aa4407fbc85
2006-11-12Yet another small bug in mem system related to flow controlRon Dreslinski
src/mem/cache/cache_impl.hh: When upgrades change to readEx make sure to allocate the block Fix dprintf --HG-- extra : convert_revision : 8700a7e47ad042c8708302620b907849c4bfdded
2006-11-12Fix functional access errors related to delayed respnoses in cachePortRon Dreslinski
src/mem/cache/base_cache.cc: On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag. src/mem/packet.cc: src/mem/packet.hh: Create a wrapper to toggle the hasData flag on delayed responses --HG-- extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
2006-11-10More fixes for functional accesses. It now makes the writeback memory leak ↵Ron Dreslinski
to crash all configs. Working on that now. src/mem/cache/base_cache.cc: Keep a list of the responders so we can search them on functional accesses. src/mem/cache/base_cache.hh: Properly put things on a list for responses so we can search the list. Also, be sure to check the outgoing ports lists on a functional access (factor some common code out there) src/mem/cache/cache_impl.hh: Properly return when the first read hit on a functional access. Make sure to call to check the other ports list of packets before forwarding it out. --HG-- extra : convert_revision : 1d21cb55ff29c15716617efc48441329707c088a
2006-11-07Fix up bus draining and add draining to the caches.Kevin Lim
src/mem/bus.cc: Fix up draining to work properly. src/mem/bus.hh: Initialize drainEvent to NULL. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: Add draining to the caches. --HG-- extra : convert_revision : 3082220a75d50876f10909f9f99bec535889f818
2006-11-02Caches return a new functional port whenever asked for one.Kevin Lim
src/mem/cache/base_cache.cc: Have caches return a new functional port whenever asked for them. I'm pretty sure this is desired behavior. Ron can correct me if it's not. --HG-- extra : convert_revision : e1fadf895a7d714968128ff900d10e86fde53387
2006-10-31Ports now have a pointer to the MemObject that owns it (can be NULL).Kevin Lim
src/cpu/simple/atomic.hh: Port now takes in the MemObject that owns it. src/cpu/simple/timing.hh: Port now takes in MemObject that owns it. src/dev/io_device.cc: src/mem/bus.hh: Ports now take in the MemObject that owns it. src/mem/cache/base_cache.cc: Ports now take in the MemObject that own it. src/mem/port.hh: src/mem/tport.hh: Ports now optionally take in the MemObject that owns it. --HG-- extra : convert_revision : 890a72a871795987c2236c65937e06973412d349
2006-10-22Clean up cache DPRINTFsSteve Reinhardt
--HG-- extra : convert_revision : f836e77efd40e25259d7794dd148696586b79a09
2006-10-22s/pktuest/request/ (all in comments)Steve Reinhardt
--HG-- extra : convert_revision : 7ce779242a15245a20322c0b6c40d02c8ddd15ad
2006-10-21Small bug fixes for timing LL/SC. Better now butSteve Reinhardt
not necessarily 100% there yet. src/mem/cache/cache_impl.hh: Generate response packet on failed store conditional. src/mem/packet.hh: Clear packet flags when reinitializing. (SATISFIED in particular is one we don't want to leave set.) --HG-- extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f
2006-10-21Just give up if a store conditional misses completelySteve Reinhardt
in the cache (don't treat as normal write miss). --HG-- extra : convert_revision : c030eb6ba25318cae422e4da31e3b802049c8c74
2006-10-21Refactor coherence state table initialization.Steve Reinhardt
--HG-- extra : convert_revision : eb36dd2cc1463e5076f4758a59cf68cc6b2bafc5
2006-10-20Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest src/mem/tport.cc: Merge PacketPtr changes --HG-- extra : convert_revision : 0329c5803a3df67af3dda89bd9d4753fd1a286d1
2006-10-20Use fixPacket function everywhere.Ron Dreslinski
Fix fixPacket assert function. Stop timing port from forwarding the request if a response was found in its queue on a read. src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: src/python/m5/objects/MemTest.py: Add parameter to configure what percentage of mem accesses are functional src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Use fix Packet function src/mem/packet.cc: Fix an assert that was checking the wrong thing src/mem/tport.cc: Properly detect if we need to do the access to the functional device --HG-- extra : convert_revision : 447cc1a9a65ddd2a41e937fb09dc0e7c74e9c75e
2006-10-20Use PacketPtr everywhereNathan Binkert
--HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
and call it packet_access.hh and fix the #includes so things compile right. --HG-- extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
2006-10-19Fix corner case on assertion.Ron Dreslinski
I need to move over to using the fixPacket function so I don't have to make the same changes everywhere. Still a functional access bug someplace I need to track down in timing mode. src/mem/cache/base_cache.cc: src/mem/cache/cache_impl.hh: Fix corner case on assertion tests/configs/memtest.py: Updated memtester with uncacheable addresses and functional accesses --HG-- extra : convert_revision : e6fa851621700ff9227b83cc5cac20af4fc8444f
2006-10-19Fix memtester to use functional access, fix cache to work functionally now ↵Ron Dreslinski
that we could test it. src/cpu/memtest/memtest.cc: Fix memtest to do functional accesses src/mem/cache/cache_impl.hh: Fix cache to handle functional accesses properly based on memtester changes Still need to fix functional accesses in timing mode now that the memtester can test it. --HG-- extra : convert_revision : a6dbca4dc23763ca13560fbf5d41a23ddf021113
2006-10-19Small changes:Ron Dreslinski
?? doesn't compile in warn statements Should have been false, where I had a true. src/cpu/o3/lsq_impl.hh: Apparently you can't have ?? in a warn statement (Something about trigraphs) src/mem/cache/cache_impl.hh: Forgot to signal atomic mode in snoopProbe --HG-- extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
2006-10-19Fixes to get single level uni-coherence to work.Ron Dreslinski
Now to try L2 caches in FS. src/mem/cache/base_cache.hh: Fix uni-coherence for atomic accesses in coherence protocol access to port src/mem/cache/cache_impl.hh: Properly handle uni-coherence src/mem/cache/coherence/simple_coherence.hh: Properly forward invalidates (not done for MSI+ protocols (assumed top level for now) src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Properly forward invalidates in atomic/timing uni-coherence --HG-- extra : convert_revision : f0f11315e8e7f32c19d92287f6f9c27b079c96f7
2006-10-19Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069
2006-10-19Always get the functional access from the highest level of cache first.Ron Dreslinski
src/mem/cache/cache_impl.hh: Get the read data from the highest level of cache on a functional access --HG-- extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
2006-10-19First cut at LL/SC support in caches (atomic mode only).Steve Reinhardt
configs/example/fs.py: Add MOESI protocol to caches (uni coherence not quite working w/FS yet). --HG-- extra : convert_revision : 7bef7d9c5b24bf7241cc810df692408837b06b86
2006-10-18Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
2006-10-18Break a lot of overly long lines.Steve Reinhardt
Factor out some asserts that were on both sides of an if/else. --HG-- extra : convert_revision : 78f0c2d76a81a98216b2f281159c6b6ea0147731
2006-10-18Get rid of doData() lines (were already commented out).Steve Reinhardt
Reindent due to resulting changes in nesting. --HG-- extra : convert_revision : 6be099d572efb618efb08fbc06d7e0e4b5b4cab2
2006-10-18Get rid of obsolete in-cache copy support.Steve Reinhardt
--HG-- extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
2006-10-17Include packet_impl.hh (need this on my laptop,Steve Reinhardt
but not on zizzer... g++ 4 thing maybe?) --HG-- extra : convert_revision : 31c49f1c55fe9daf6365411bfb5bb7f6ccc8032d
2006-10-17Fixes for uni-coherence in timing mode for FS.Ron Dreslinski
Still a bug in atomic uni-coherence in FS. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Make CPU models handle coherence requests src/mem/cache/base_cache.cc: Properly signal coherence CSHRs src/mem/cache/coherence/uni_coherence.cc: Only deallocate once --HG-- extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
2006-10-17Fixes to cache eliminating the assumption that the Packet is still valid ↵Ron Dreslinski
after sending out a request. Still need to rework upgrades into this system, but works for now. src/mem/cache/base_cache.cc: Re order code to be more readable src/mem/cache/base_cache.hh: Be sure to delete the copy on a bus block src/mem/cache/cache_impl.hh: Be sure to remove the copy on a writeback success src/mem/cache/miss/mshr_queue.cc: Demorgans to make it easier to understand src/mem/tport.cc: Delete writebacks --HG-- extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
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