gem5 - gem5

Age	Commit message (Expand)	Author
2014-09-20	mem: Remove the GHB prefetcher from the source tree	Mitch Hayenga
2014-09-19	misc: Remove assertions ensuring unsigned values >= 0	Andreas Hansson
2014-09-19	mem: Add checks to sendTimingReq in cache	Andreas Hansson
2014-09-09	misc: Fix a number of unitialised variables and members	Andreas Hansson
2014-06-27	mem: write streaming support via WriteInvalidate promotion	Curtis Dunham
2014-09-03	mem: Fix a bug in the cache port flow control	Andreas Hansson
2014-05-13	cpu, mem: Make software prefetches non-blocking	Curtis Dunham
2014-09-03	cache: Fix handling of LL/SC requests under contention	Geoffrey Blake
2014-09-03	arch: Cleanup unused ISA traits constants	Andreas Hansson
2014-08-13	mem: Properly set cache block status fields on writebacks	Mitch Hayenga
2014-07-28	mem: refactor LRU cache tags and add random replacement tags	Anthony Gutierrez
2014-05-09	mem: Squash prefetch requests from downstream caches	Mitch Hayenga
2014-04-01	mem: Don't print out the data of a cache block	Mitch Hayenga
2014-03-07	mem: Fix incorrect assert failure in the Cache	Prakash Ramrakhyani
2014-02-18	mem: Filter cache snoops based on address ranges	Andreas Hansson
2014-01-29	mem: Add additional tolerance to stride prefetcher	Mitch Hayenga
2014-01-29	mem: Allowed tagged instruction prefetching in stride prefetcher	Mitch Hayenga
2014-01-29	mem: prefetcher: add options, support for unaligned addresses	Mitch Hayenga ext:(%2C%20Amin%20Farmahini%20%3Caminfar%40gmail.com%3E)
2014-01-28	mem: Remove redundant findVictim() input argument	Amin Farmahini
2014-01-24	mem: Add support for a security bit in the memory system	Giacomo Gabrielli
2014-01-24	Cache: Collect very basic stats on tag and data accesses	Timothy M. Jones
2014-01-24	mem: per-thread cache occupancy and per-block ages	Dam Sunwoo
2014-01-24	mem: track per-request latencies and access depths in the cache hierarchy	Matt Horsnell
2013-10-17	cpu: add consistent guarding to *_impl.hh files.	Matt Horsnell
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson
2013-07-18	mem: Set the cache line size on a system level	Andreas Hansson
2013-07-18	mem: Add cache class destructor to avoid memory leaks	Xiangyu Dong
2013-06-27	mem: Reorganize cache tags and make them a SimObject	Prakash Ramrakhyani
2013-06-27	mem: Remove the cache builder	Andreas Hansson
2013-06-27	mem: Align cache timing to clock edges	Andreas Hansson
2013-06-27	mem: Cycles converted to Ticks in atomic cache accesses	Andreas Hansson
2013-06-27	mem: Remove a redundant heap allocation for a snoop packet	Andreas Hansson
2013-05-30	mem: Spring cleaning of MSHR and MSHRQueue	Andreas Hansson
2013-05-30	mem: Fix MSHR print format	Andreas Hansson
2013-04-22	mem: Adding verbose debug output in the memory system	Uri Wiener
2013-03-27	mem: Fix cache latency bug	Mitch Hayenga
2013-03-26	mem: Cancel cache retry event when blocking port	Rene de Jong
2013-02-19	mem: Fix sender state bug and delay popping	Andreas Hansson
2013-02-19	scons: Fix up numerous warnings about name shadowing	Andreas Hansson
2013-02-19	mem: Enforce strict use of busFirst- and busLastWordTime	Andreas Hansson
2013-02-19	mem: Change accessor function names to match the port interface	Andreas Hansson
2013-02-19	mem: Make packet bus-related time accounting relative	Andreas Hansson
2013-02-19	mem: Add deferred packet class to prefetcher	Andreas Hansson
2013-02-19	sim: Make clock private and access using clockPeriod()	Andreas Hansson
2013-02-19	mem: Fix SenderState related cache deadlock	Sascha Bischoff
2013-02-19	mem: Add predecessor to SenderState base class	Andreas Hansson
2013-02-15	mem: Tighten up cache constness and scoping	Andreas Hansson
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-01-28	cache: remove drainManager because it's not used	Anthony Gutierrez
2013-01-08	mem: Make LL/SC locks fine grained	Mitch Hayenga