gem5 - gem5

Age	Commit message (Expand)	Author
2012-05-10	Cache: restructure code that actually isn't a loop	Ali Saidi
2012-05-10	gem5: fix some iterator use and erase bugs	Ali Saidi
2012-05-10	gem5: Fix a number of incorrect case statements	Ali Saidi
2012-05-10	Cache: Panic if you attempt to create a checkpoint with a cache in the system	Ali Saidi
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-22	MEM: Split SimpleTimingPort into PacketQueue and ports	Andreas Hansson
2012-03-09	cache: Allow main memory to be at disjoint address ranges.	Ali Saidi
2012-03-01	Cache: Fix an issue with LRU when bonus block is used to complete transaction.	Ali Saidi
2012-02-24	MEM: Simplify cache ports preparing for master/slave split	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-02-12	mem: fix cache stats to use request ids correctly	Dam Sunwoo
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-12	prefetcher: Make prefetcher a sim object instead of it being a parameter on c...	Mrinmoy Ghosh
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-31	MEM: Remove the otherPort from the cache ports	Andreas Hansson
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	MEM: Remove the functional ports from the memory system	William Wang
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Remove Port removeConn and MemObject deletePortRefs	Andreas Hansson
2012-01-17	MEM: Simplify ports by removing EventManager	Andreas Hansson
2012-01-17	MEM: Differentiate functional cache accesses from CPU and memory	Andreas Hansson
2012-01-07	Merge with main repository.	Gabe Black
2011-11-18	SE/FS: Get rid of includes of config/full_system.hh.	Gabe Black
2011-11-07	SE/FS: Get rid of FULL_SYSTEM in mem.	Gabe Black
2011-10-31	GCC: Get everything working with gcc 4.6.1.	Gabe Black
2011-09-13	Prefetch: Don't prefetch if address is in the write queue.	Ali Saidi
2011-09-01	Fix build for gcc-4.2 opt/fast	Lisa Hsu
2011-08-19	Mem: Put prefetcher notify call before packet is deleted.	Ali Saidi
2011-08-19	Prefetcher: Fix some memory leaks with the prefetcher.	Ali Saidi
2011-07-15	Mem: Fix issue with prefetches originating at non-L1 caches getting stale data	Ali Saidi
2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert
2011-04-19	stats: rename stats so they can be used as python expressions	Nathan Binkert
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to n...	Ali Saidi
2011-02-23	Includes: Don't include isa_traits.hh and use the TheISA namespace unless rea...	Ali Saidi
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-11-19	SCons: Support building without an ISA	Ali Saidi
2010-10-18	cache: minor SC assertion fix	Steve Reinhardt
2010-10-13	Mem: Change the CLREX flag to CLEAR_LL.	Gabe Black
2010-09-21	cache: improve coherence handling of writebacks	Steve Reinhardt
2010-09-10	style: fix sorting of includes and whitespace in some files	Nathan Binkert
2010-09-09	cache: fail SC when invalidated while waiting for bus	Steve Reinhardt
2010-09-09	mem: fix functional accesses to deal with coherence change	Steve Reinhardt
2010-09-09	cache: coherence protocol enhancements & bug fixes	Steve Reinhardt