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2018-04-13mem-cache: Add MoveToTail to FALRUDaniel R. Carvalho
FALRU was missing MoveToTail functionality within its invalidate function, and MoveToHead was doing unnecessary passes when the moved block was the head already. Besides, added some comments to make the code understandable. Change-Id: I2430d82b5d53c88b102a62610ea38b46d6e03a55 Reviewed-on: https://gem5-review.googlesource.com/9541 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-06mem: Remove unused 'using namespace'Daniel R. Carvalho
Removal of unused/barely used 'using namespace' from C++ files. Change-Id: I66dc548c04506db2e41180b9ea7ab5abd7d5375a Reviewed-on: https://gem5-review.googlesource.com/9601 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-06mem-cache: Move insertBlock functionality in FALRUDaniel R. Carvalho
Block insertion is being done in the getCandidates function, while the insertBlock function does not do anything. Besides, BaseTags' stats weren't being updated. Change-Id: Iadab9c1ea61519214f66fa24c4b91c4fc95604c0 Reviewed-on: https://gem5-review.googlesource.com/8882 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-06mem-cache: Create LIP Replacement PolicyDaniel R. Carvalho
Implementation of a LRU Insertion Policy replacement policy. Change-Id: I1a9aa0091ff2cdc1b1652c1d5ec7a3b33fba5b44 Reviewed-on: https://gem5-review.googlesource.com/9002 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-06mem-cache: Create BIP Replacement PolicyDaniel R. Carvalho
Implementation of a Bimodal Insertion Policy replacement policy. Change-Id: Ife058d0d4310dbcb35858348006189f0b2bf7c37 Reviewed-on: https://gem5-review.googlesource.com/9003 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-05mem-cache: Use Packet functions to write data blocksDaniel R. Carvalho
Instead of using raw memcpy, use the proper writer functions from the Packet class in Cache. Fixed typos in comments of these functions. Change-Id: I156a00989c6cbaa73763349006a37a18243d6ed4 Reviewed-on: https://gem5-review.googlesource.com/9661 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-30mem-cache: Remove unused return value from the recvTimingReq funcNikos Nikoleris
The recvTimingReq function in the cache always returns true. This changeset removes the return value. Change-Id: I00dddca65ee7224ecfa579ea5195c841dac02972 Reviewed-on: https://gem5-review.googlesource.com/8289 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-30mem-cache: Fix FALRU data block seg faultDaniel R. Carvalho
FALRU didn't initialize the blocks' data, causing seg faults. This patch does not make FALRU functional yet. Change-Id: I10cbcf5afc3f8bc357eeb8b7cb46789dec47ba8b Reviewed-on: https://gem5-review.googlesource.com/9302 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-30mem-cache: Create LFU replacement policyDaniel R. Carvalho
Implementation of a Least Frequently Used replacement policy. Change-Id: I772afccd3a7955777e53d59341e922718db44e5c Reviewed-on: https://gem5-review.googlesource.com/8890 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-30mem-cache: Create RRIP Replacement PolicyDaniel R. Carvalho
Implementation of a Re-Reference Interval Prediction replacement policy. Change-Id: Iba716eb5df2bf2be156e765f889d94f6ad00c91b Reviewed-on: https://gem5-review.googlesource.com/8981 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-03-30mem-cache: Create BRRIP replacement policyDaniel R. Carvalho
Implementation of a Bimodal Re-Reference Interval Prediction replacement policy. Change-Id: I25d4a59a60ef7ac496c66852e394fd6cbaf50912 Reviewed-on: https://gem5-review.googlesource.com/8891 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23mem-cache: fix missing overrides in repl policiesJason Lowe-Power
Change-Id: I67759a4532e8a46c1643d4c3a9c546ad6b565b81 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/9321 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23mem-cache: Create FIFO replacement policyDaniel R. Carvalho
Implementation of a First-In, First-Out replacement policy. Change-Id: Id234ec9d29c092dd4516e609da14b8a75a96b5e4 Reviewed-on: https://gem5-review.googlesource.com/8888 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-23mem-cache: Fix MRU rebaseDaniel R. Carvalho
Rebase of MRU missed a const qualifier, introducing a compilation error. Change-Id: Ia25aa30523613a1a87593a353abe439946656f63 Reviewed-on: https://gem5-review.googlesource.com/9301 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-22mem-cache: Create MRU replacement policyDaniel R. Carvalho
Implementation of a Most Recently Used replacement policy. Change-Id: Id52cb247ca25d4523dcc53490d113695dac6a3f1 Reviewed-on: https://gem5-review.googlesource.com/8889 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-22mem-cache: Split array indexing and replacement policies.Daniel R. Carvalho
Replacement policies (LRU, Random) are currently considered as array indexing methods, but have completely different functionalities: - Array indexers determine the possible locations for block allocation. This information is used to generate replacement candidates when conflicts happen. - Replacement policies determine which of the replacement candidates should be evicted to make room for new allocations. For this reason, they were split into different classes. Advantages: - Easier and more straightforward to implement other replacement policies (RRIP, LFU, ARC, ...) - Allow easier future implementation of cache organization schemes As now we can't assure the use of sets, the previous way to create a true LRU is not viable. Now a timestamp_bits parameter controls how many bits are dedicated for the timestamp, and a true LRU can be achieved through an infinite number of bits (although a few bits suffice in practice). Change-Id: I23750db121f1474d17831137e6ff618beb2b3eda Reviewed-on: https://gem5-review.googlesource.com/8501 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-21mem-cache: Allow clean operations when block allocation failsNikos Nikoleris
Block allocation can fail when there is an in-service MSHR that operates on the victim block. This can happed due to: * an upgrade operation: a request that needs a writable copy of the block finds a shared (non-writable) copy of the block in the cache and has allocates an MSHR for the pending upgrade operation, or * a clean operation: a clean request finds a dirty copy of the block and allocates an MSHR for the pending clean operation. This changes relaxes an assertion to allow for the 2nd case (cache clean operations). Change-Id: Ib51482160b5f2b3702ed744b0eac2029d34bc9d4 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9021 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-09mem-cache: Use CacheBlk parameter on address regenerationDaniel R. Carvalho
Skewed caches need to know the way to regenerate a block address. Change-Id: I62c61ac9509eff2f37bad36862751956db7a6e40 Reviewed-on: https://gem5-review.googlesource.com/8782 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-08mem-cache: Fix missing overridesJason Lowe-Power
clang doesn't like inconsistent overrides. Add override to all overidden functions in lru.hh Change-Id: I100ff4a7d90757439afee879ff9838c15f5c0b1d Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/8861 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-07mem-cache: Make the block invalidate functions virtualNikos Nikoleris
This change makes the cache block invalidation function in the BaseTags and CacheBlk class virtual to enable derived classes. Change-Id: I2e64b01c6ca637f16d10474fc8b08eeec3f23453 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8287 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-07mem-cache: Make invalidate a common function between tag classesNikos Nikoleris
invalidate was defined as a separate function in the base associative and fully-associative tags classes although both functions should implement identical functionality. This patch moves the invalidate function in the base tags class. Change-Id: I206ee969b00ab9e05873c6d87531474fcd712907 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8286 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-07mem-cache: Allow prefetchers to override setCache.Xiaoyu Ma
This lets them hook setCache, perhaps to set up additional state based on the set cache. Change-Id: Ic3b34fa43d052c71e8ef733a57fe47c70899cd27 Reviewed-on: https://gem5-review.googlesource.com/8701 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-06mem-cache: Fix bug generated by 8282Daniel R. Carvalho
Merge 1ae7fced4d32898531a6875a339ef00e43e20e66 generated a bug in tagsInUse calculation. Change-Id: I079e327a0a26a7968f2ed8e433dd6e790c80998b Reviewed-on: https://gem5-review.googlesource.com/8781 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-06mem-cache: Populate whenReady for blocks filled from writebacksNikos Nikoleris
Writebacks write data to either an existing block or a newly allocated block. In either case we need to populate the whenReady field of the block which will determine when the new value can be used. Change-Id: I5788fad0b8086a1be96714639bf6a9470b334926 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8285 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-06mem-cache: Use findBlock() in accessBlock()Daniel R. Carvalho
Use placement policy specific block search within generic access. Change-Id: I6070035e6e00595bcf073d4011f78a55ba7e7a8a Reviewed-on: https://gem5-review.googlesource.com/8721 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-05mem-cache: Remove redundant block initialization on allocationNikos Nikoleris
Change-Id: I7496e12e6a517529316c480d5f6e2ade601f0e2d Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8282 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-02mem-cache: Remove mumBlock redundant initialiation from FALRUNikos Nikoleris
Change-Id: Id3afec0a62446d6d0f44ccb655032343037637e0 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8281 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-02mem-cache: Populate the secure bit when the temp block is filledNikos Nikoleris
The secure bit should be set when we fill a block with data from a secure location, as indicated by the packet that triggers the fill. This patch fixes a bug in which the cache wouldn't populate the secure bit when filling the temp block. Change-Id: I95c706146449804ff42b205b25dd79750f3e882a Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8284 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-02mem-cache: Remove unnecessary block initialization on writebackNikos Nikoleris
Change-Id: Ia9b825bcbb8d326705f74c15a93a88703153ba5a Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8283 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-03-01mem-cache: Remove extra block init in BaseSetAssocDaniel R. Carvalho
Removed extra initialization of cache block just after they have been created and organized the comments. Change-Id: I75c1beaf0489e3e530fd8cbff2739dc7593e3e6f Reviewed-on: https://gem5-review.googlesource.com/8661 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-03-01mem-cache: Vectorize C arrays in BaseSetAssoc.Daniel R. Carvalho
Transform BaseSetAssoc's arrays into C++ vectors to avoid unnecessary resource management. Change-Id: I656f42f29e5f9589eba491b410ca1df5a64f2f34 Reviewed-on: https://gem5-review.googlesource.com/8621 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-02-24mem-cache: Fix CacheSet memory leakDaniel R. Carvalho
CacheSet blocks were being allocated but never freed. Used vector to avoid using pure C array. Change-Id: I6f32fa5a305ff4e1d7602535026c1396764102ed Reviewed-on: https://gem5-review.googlesource.com/8603 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-02-08mem-cache: Make cache warmup percentage a parameter.Daniel R. Carvalho
The warmupPercentage is the percentage of different tags (based on the cache size) that need to be touched in order to warm up the cache. If Warmup failed (i.e., not enough tags were touched), warmup_cycle = 0. The warmup is not being taken into account to calculate the stats (i.e., stats acquisition starts before cache is warmed up). Maybe in the future this functionality should be added. Change-Id: I2b93a99c19fddb99a4c60e6d4293fa355744d05e Reviewed-on: https://gem5-review.googlesource.com/8061 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-02-07mem-cache: Only pendingModified MSHRs can satisfy CMO snoopsNikos Nikoleris
We set the satisfied flag when a cache clean request encounters: 1) a block with the dirty bit set, or 2) a pending modified MSHR which means that the cache will get copy of the block that will be soon modified. This changeset fixes a previous bug that set the satisfied flag on snooping MSHR hits even the pendingModified flags was not set. Change-Id: I4968c4820997be5cc1238148eea12a1ba39837d4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7822 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-02-07mem-cache: Cleaned blocks should be marked as not writableNikos Nikoleris
A writeclean packet writes a dirty block to the memory below and therefore sets the dirty flag for the block when the memory below is a cache. If the block was also marked as writable it can satisfy future write requests without further requests/snoops. This can lead to multiple copies of the same block marked as dirty which is not allowed. This changeset clears the writable flag from the cleaned block to prevent the cache from satisfying future write requests without sending a downstream request. Change-Id: I14d3c62fd33f81b1a8ba62374c8565ccab00a6fe Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/7821 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-02-06mem-cache: Remove extra numSets zero check.Daniel R. Carvalho
numSets is unsigned, so it cannot be lower than 0. Besides, isPowerOf2(0) is false by definition (and implemmentation*), so there is no need for the double check. * As presented in base/intmath.hh Change-Id: I3f6296694a937434feddc7ed21f11c2a6fdfc5a9 Reviewed-on: https://gem5-review.googlesource.com/7901 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-02-06mem: Standardize mem folder header guardsDaniel R. Carvalho
Standardize all header guards in the mem directory according to the most frequent patterns. In general they have the form: mem: __FOLDER_TREE_FILE_NAME_HH__ ruby: __FOLDER_TREE_FILENAME_HH__ Change-Id: I983853e292deb302becf151bf0e970057dc24774 Reviewed-on: https://gem5-review.googlesource.com/7881 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-01-09mem-cache: Prune unnecessary writebacks in exclusive cachesNikos Nikoleris
Exclusive caches use the tempBlock to fill for responses from a downstream cache. The reason for this is that they only pass the block to the cache above without keeping a copy. When all requests are serviced the block is immediately invalidated unless it is dirty, in which case it has to be written back to the memory below. To avoid unnecessary writebacks, this changeset forces mostly exclusive caches to issuse requests that can only fetch clean data when possible. Reported-by: Quereshi Muhammad Avais <avais@kaist.ac.kr> Change-Id: I01b377563f5aa3e12d22f425a04db7c023071849 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5061 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05mem: Co-ordination of CMOs in the xbarNikos Nikoleris
A clean packet request serving a cache maintenance operation (CMO) visits all memories down to the specified xbar. The visited caches invalidate their copy (if the CMO is invalidating) and if a dirty copy is found a write packet writes the dirty data to the memory level below the specified xbar. A response is send back when all the caches are clean and/or invalidated and the specified xbar has seen the write packet. This patch adds the following functionality in the xbar: 1) Accounts for the cache clean requests that go through the xbar 2) Generates the cache clean response when both the cache clean request and the corresponding writeclean packet has crossed the destination xbar. Previously transactions in the xbar were identified using the pointer of the original request. Cache clean transactions comprise of two different packets, the clean request and the writeclean, and therefore have different request pointers. This patch adds support for custom transaction IDs that by default take the value of the request pointer but can be overriden by the contructor. This allows the clean request and writeclean share the same id which the coherent xbar uses to co-ordinate them and send the response in a timely manner. Change-Id: I80db76386a1caded38dc66e6e18f930c3bb800ff Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5051 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Add support for handling CMOs in the MSHRsNikos Nikoleris
To add support for cache maintenance operations (CMOs) in the MSHRs, this change adds the following functionality: - If a CMO request hits in the MSHRs, we deferred as we can't coalesce it with any other requests. - When we promote any deferred targets, we promote them in order and stop if we encounter a CMO request. If the CMO request is at the beginning of the deferred targets list it will be the only promoted target. Change-Id: I10d1f7e16bd6d522d917279c5d408a3f0cee4286 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5050 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Add support for CMOs in the cacheNikos Nikoleris
This change adds support for maintenance operations (CMOs) in the cache. The supported memory operations clean and/or invalidate a cache block as specified by its VA to the specified xbar (PoU, PoC). A cache maintenance packet visits all memories down to the specified xbar. Caches need to invalidate their copy if it is an invalidating CMO. If it is (additionally) a cleaning CMO and a dirty copy exists, the cache cleans it with a WriteClean request. Change-Id: Ibf31daa7213925898f3408738b11b1dd76c90b79 Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5049 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Promote deferred targets only when the block is validNikos Nikoleris
When a response indicates that there are no other sharers of the block, the cache can promote its copy of the block to writable and potential service deferred targets even if the request didn't ask for a writable copy. Previously, a response would guarantee the presence of the block in the cache. A response could either be filling, upgrading or a response to an invalidation due to a pending whole line write. Responses to cache maintenance invalidations break this assumption. This change adds an extra check to make sure that the block was already valid or that the response is filling before promoting the block. Change-Id: I6839f683a05d4dad4205c23f365a925b7b05e366 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5048 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Support for specifying the destination of a WriteCleanNikos Nikoleris
Previously, WriteClean packets would always write to the first memory below unless the memory was unable to allocate in which case it would be forwarded further below. This change adds support for specifying the destination of a WriteClean packet. The cache annotates the request with the specified destination and marks the packet as write-through upon its creation. The coherent xbar checks packets for their destination and resets the write-through flag when necessary e.g., the coherent xbar that is set as the PoC will reset the write-through flag for packets to the PoC. Change-Id: I84b653f5cb6e46e97e09508649a3725d72d94606 Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5046 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-12-05mem: Add support for WriteClean packets in the memory systemNikos Nikoleris
This change adds support for creating and handling WriteClean packets. The WriteClean operation is almost identical to a WritebackDirty with the exception that the cache generating a WriteClean retains a copy of the block. Change-Id: I63c8de62919fad0f9547d412f8266aa4292ebecd Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-on: https://gem5-review.googlesource.com/5045 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-05mem-cache: Add support for checking whether a cache is busyNikos Nikoleris
This changeset adds support for checking whether the cache is currently busy and a timing request would be rejected. Change-Id: I5e37b011b2387b1fa1c9e687b9be545f06ffb5f5 Reviewed-on: https://gem5-review.googlesource.com/5042 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
These files aren't a collection of miscellaneous stuff, they're the definition of the Logger interface, and a few utility macros for calling into that interface (panic, warn, etc.). Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1 Reviewed-on: https://gem5-review.googlesource.com/6226 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2017-08-08mem-cache: Delete squashed HWPrefetchesPau Cabre
Request and Packet for squashed HWPrefetches were not deleted Change-Id: I9b66bb01b8ed6a5ddfaaa8739a68165dc4a7006c Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/4340 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-06-27mem-cache: Add missing overrides to BaseCacheAndreas Sandberg
Change-Id: I6a3a57e3067c247bd6ce6f01ac9459883f4aae2c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3880 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-06-20mem: Replace EventWrapper use with EventFunctionWrapperSean Wilson
NOTE: With this change there is a possibility for `DRAMCtrl::Rank`s event names to not properly match the rank they were generated by. This could occur if the public rank member is modified after the Rank's construction. A patch would mean refactoring Rank and `DRAMCtrl`b to privatize many of the members of Rank behind getters. Change-Id: I7b8bd15086f4ffdfd3f40be4aeddac5e786fd78e Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3745 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2017-03-03mem: Make blkAlign a common function between all tag classesNikos Nikoleris
blkAlign was defined as a separate function in the base associative and fully-associative tags classes although both functions implemented identical functionality. This patch moves the blkAlign in the base tags class. Change-Id: I3d415d0e62bddeec7ce0d559667e40a8c5fdc2d4 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>