gem5 - gem5

Age	Commit message (Expand)	Author
2013-07-18	mem: Add cache class destructor to avoid memory leaks	Xiangyu Dong
2013-06-27	mem: Reorganize cache tags and make them a SimObject	Prakash Ramrakhyani
2013-06-27	mem: Remove the cache builder	Andreas Hansson
2013-06-27	mem: Align cache timing to clock edges	Andreas Hansson
2013-06-27	mem: Cycles converted to Ticks in atomic cache accesses	Andreas Hansson
2013-06-27	mem: Remove a redundant heap allocation for a snoop packet	Andreas Hansson
2013-05-30	mem: Spring cleaning of MSHR and MSHRQueue	Andreas Hansson
2013-05-30	mem: Fix MSHR print format	Andreas Hansson
2013-04-22	mem: Adding verbose debug output in the memory system	Uri Wiener
2013-03-27	mem: Fix cache latency bug	Mitch Hayenga
2013-03-26	mem: Cancel cache retry event when blocking port	Rene de Jong
2013-02-19	mem: Fix sender state bug and delay popping	Andreas Hansson
2013-02-19	scons: Fix up numerous warnings about name shadowing	Andreas Hansson
2013-02-19	mem: Enforce strict use of busFirst- and busLastWordTime	Andreas Hansson
2013-02-19	mem: Change accessor function names to match the port interface	Andreas Hansson
2013-02-19	mem: Make packet bus-related time accounting relative	Andreas Hansson
2013-02-19	mem: Add deferred packet class to prefetcher	Andreas Hansson
2013-02-19	sim: Make clock private and access using clockPeriod()	Andreas Hansson
2013-02-19	mem: Fix SenderState related cache deadlock	Sascha Bischoff
2013-02-19	mem: Add predecessor to SenderState base class	Andreas Hansson
2013-02-15	mem: Tighten up cache constness and scoping	Andreas Hansson
2013-02-15	sim: Add a system-global option to bypass caches	Andreas Sandberg
2013-01-28	cache: remove drainManager because it's not used	Anthony Gutierrez
2013-01-08	mem: Make LL/SC locks fine grained	Mitch Hayenga
2013-01-07	mem: Fix guest corruption when caches handle uncacheable accesses	Andreas Sandberg
2013-01-07	mem: Remove the IIC replacement policy	Andreas Sandberg
2013-01-07	sim: Fatal if a clocked object is set to have a clock of 0	Andreas Hansson
2013-01-07	cache: add note about where conflicts are handled	Ali Saidi
2012-11-02	mem: Add support for writing back and flushing caches	Andreas Sandberg
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-10-15	Mem: Use cycles to express cache-related latencies	Andreas Hansson
2012-09-25	MEM: Put memory system document into doxygen	Djordje Kovacevic
2012-09-25	Cache: add a response latency to the caches	Mrinmoy Ghosh
2012-09-19	AddrRange: Transition from Range<T> to AddrRange	Andreas Hansson
2012-09-11	clang: Fix issues identified by the clang static analyzer	Andreas Hansson
2012-09-11	Cache: Split invalidateBlk up to seperate block vs. tags	Lena Olson
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-22	Port: Extend the QueuedPort interface and use where appropriate	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-07-27	cache: don't allow dirty data in the i-cache	Anthony Gutierrez
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Port: Make getAddrRanges const	Andreas Hansson
2012-07-09	Port: Add isSnooping to slave port (asking master port)	Andreas Hansson
2012-07-09	Port: Move retry from port base class to Master/SlavePort	Andreas Hansson
2012-07-09	Fix: Address a few benign memory leaks	Andreas Hansson
2012-06-29	Cache: Fix the LRU policy for classic memory hierarchy	Lena Olson