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path: root/src/mem/cache
AgeCommit message (Expand)Author
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2013-02-19mem: Fix SenderState related cache deadlockSascha Bischoff
2013-02-19mem: Add predecessor to SenderState base classAndreas Hansson
2013-02-15mem: Tighten up cache constness and scopingAndreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-01-28cache: remove drainManager because it's not usedAnthony Gutierrez
2013-01-08mem: Make LL/SC locks fine grainedMitch Hayenga
2013-01-07mem: Fix guest corruption when caches handle uncacheable accessesAndreas Sandberg
2013-01-07mem: Remove the IIC replacement policyAndreas Sandberg
2013-01-07sim: Fatal if a clocked object is set to have a clock of 0Andreas Hansson
2013-01-07cache: add note about where conflicts are handledAli Saidi
2012-11-02mem: Add support for writing back and flushing cachesAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25MEM: Put memory system document into doxygenDjordje Kovacevic
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-11clang: Fix issues identified by the clang static analyzerAndreas Hansson
2012-09-11Cache: Split invalidateBlk up to seperate block vs. tagsLena Olson
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-07-27cache: don't allow dirty data in the i-cacheAnthony Gutierrez
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-06-29Cache: Fix the LRU policy for classic memory hierarchyLena Olson
2012-06-29Mem: fix master id assertion in cache_impl.hhDam Sunwoo
2012-06-29Cache: Only invalidate a line in the cache when an uncacheable write is seen.Ali Saidi
2012-06-07mem: Delay deleting of incoming packets by one call.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-05-30Bus: Turn the PortId into a transport function parameterAndreas Hansson
2012-05-30Packet: Unify the use of PortID in packet and portAndreas Hansson
2012-05-24Cache: Remove dangling doWriteback declarationAndreas Hansson
2012-05-10Cache: restructure code that actually isn't a loopAli Saidi
2012-05-10gem5: fix some iterator use and erase bugsAli Saidi
2012-05-10gem5: Fix a number of incorrect case statementsAli Saidi
2012-05-10Cache: Panic if you attempt to create a checkpoint with a cache in the systemAli Saidi
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
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