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path: root/src/mem/cache
AgeCommit message (Expand)Author
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-10-15Port: Add protocol-agnostic ports in the port hierarchyAndreas Hansson
2012-10-15Fix: Address a few minor issues identified by cppcheckAndreas Hansson
2012-10-15Mem: Use cycles to express cache-related latenciesAndreas Hansson
2012-09-25MEM: Put memory system document into doxygenDjordje Kovacevic
2012-09-25Cache: add a response latency to the cachesMrinmoy Ghosh
2012-09-19AddrRange: Transition from Range<T> to AddrRangeAndreas Hansson
2012-09-11clang: Fix issues identified by the clang static analyzerAndreas Hansson
2012-09-11Cache: Split invalidateBlk up to seperate block vs. tagsLena Olson
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-22Port: Extend the QueuedPort interface and use where appropriateAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-07-27cache: don't allow dirty data in the i-cacheAnthony Gutierrez
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Port: Make getAddrRanges constAndreas Hansson
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
2012-07-09Port: Move retry from port base class to Master/SlavePortAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-06-29Cache: Fix the LRU policy for classic memory hierarchyLena Olson
2012-06-29Mem: fix master id assertion in cache_impl.hhDam Sunwoo
2012-06-29Cache: Only invalidate a line in the cache when an uncacheable write is seen.Ali Saidi
2012-06-07mem: Delay deleting of incoming packets by one call.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-05-30Bus: Turn the PortId into a transport function parameterAndreas Hansson
2012-05-30Packet: Unify the use of PortID in packet and portAndreas Hansson
2012-05-24Cache: Remove dangling doWriteback declarationAndreas Hansson
2012-05-10Cache: restructure code that actually isn't a loopAli Saidi
2012-05-10gem5: fix some iterator use and erase bugsAli Saidi
2012-05-10gem5: Fix a number of incorrect case statementsAli Saidi
2012-05-10Cache: Panic if you attempt to create a checkpoint with a cache in the systemAli Saidi
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-01Cache: Fix an issue with LRU when bonus block is used to complete transaction.Ali Saidi
2012-02-24MEM: Simplify cache ports preparing for master/slave splitAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-31MEM: Remove the otherPort from the cache portsAndreas Hansson
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang