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path: root/src/mem/cache
AgeCommit message (Expand)Author
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
2007-05-27Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
2007-05-22Fix getDeviceAddressRanges() to get snooping right.Steve Reinhardt
2007-05-22Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-22Another pass of minor changes in preparation for new protocol.Steve Reinhardt
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
2007-05-14Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
2007-05-14add uglyiness to fix dmasAli Saidi
2007-05-13Eliminate unused PacketPtr from BaseCache'sSteve Reinhardt
2007-05-13Split BaseCache::CacheEvent into RequestEvent and ResponseEvent.Steve Reinhardt
2007-05-10remove hit_latency and make latency do the right thingAli Saidi
2007-05-09add a backoff algorithm when nacks are received by devicesAli Saidi
2007-04-04The MemoryObject tha owns a port should delete it if it so chooses when delet...Ali Saidi
2007-03-28Call compare and Swap on the target, not the response.Ron Dreslinski
2007-03-27Merge zizzer:/bk/newmemRon Dreslinski
2007-03-27First Pass At Cmp/Swap in cachesRon Dreslinski
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-233 memory system fixes:Kevin Lim
2007-03-12Clean up more memory leaksRon Dreslinski
2007-03-12Fix some of the memory leaks related to writebacksRon Dreslinski
2007-03-10Rework the way SCons recurses into subdirectories, making itNathan Binkert
2007-03-08stop m5 from leaking like a sieveAli Saidi
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2007-02-07Merge zizzer.eecs.umich.edu:/bk/newmemSteve Reinhardt
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
2007-02-06Minor DPRINTF fixes.Steve Reinhardt
2007-02-06Fix for LL/SC that Ron sent me.Kevin Lim
2007-01-26make our code a little more standards compliantAli Saidi
2006-12-18Streamline Cache/Tags interface: get rid of redundant functions,Steve Reinhardt
2006-12-18No need to template prefetcher on cache TagStore type.Steve Reinhardt
2006-12-18Get rid of generic CacheTags object (fold back into Cache).Steve Reinhardt
2006-12-13Split CachePort class into CpuSidePort and MemSidePortSteve Reinhardt
2006-12-05Don't compress data on writebacks unless it's actually necessary.Steve Reinhardt
2006-12-04Turn cache MissQueue/BlockingBuffer into virtual objectSteve Reinhardt
2006-12-02Make cache compression policy a runtime virtual thingSteve Reinhardt
2006-11-28Remove assertion. It's not needed and messes up writebacks when a 2 level ca...Kevin Lim
2006-11-22Do a functional access to levels above on a read as a temporary solution for ...Ron Dreslinski
2006-11-13Fix a bug to handle the fact that a CPU can send Functional accesses while a ...Ron Dreslinski
2006-11-13If we didn't satisfy all targets, reset the packet we are requesting with.Ron Dreslinski
2006-11-13Since cpus now send out snoop ranges, remove it from the cache.Ron Dreslinski
2006-11-12Handle packets being deleted by lower level properly.Ron Dreslinski
2006-11-12Don't insert reponses into the list more than onceRon Dreslinski
2006-11-12Move code before a early return to make sure it is executed on all pathsRon Dreslinski
2006-11-12Yet another small bug in mem system related to flow controlRon Dreslinski
2006-11-12Fix functional access errors related to delayed respnoses in cachePortRon Dreslinski
2006-11-10More fixes for functional accesses. It now makes the writeback memory leak t...Ron Dreslinski
2006-11-07Fix up bus draining and add draining to the caches.Kevin Lim
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