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path: root/src/mem/cache
AgeCommit message (Expand)Author
2012-06-05sim: Remove FastAllocAli Saidi
2012-05-30Bus: Turn the PortId into a transport function parameterAndreas Hansson
2012-05-30Packet: Unify the use of PortID in packet and portAndreas Hansson
2012-05-24Cache: Remove dangling doWriteback declarationAndreas Hansson
2012-05-10Cache: restructure code that actually isn't a loopAli Saidi
2012-05-10gem5: fix some iterator use and erase bugsAli Saidi
2012-05-10gem5: Fix a number of incorrect case statementsAli Saidi
2012-05-10Cache: Panic if you attempt to create a checkpoint with a cache in the systemAli Saidi
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-22MEM: Split SimpleTimingPort into PacketQueue and portsAndreas Hansson
2012-03-09cache: Allow main memory to be at disjoint address ranges.Ali Saidi
2012-03-01Cache: Fix an issue with LRU when bonus block is used to complete transaction.Ali Saidi
2012-02-24MEM: Simplify cache ports preparing for master/slave splitAndreas Hansson
2012-02-13MEM: Introduce the master/slave port roles in the Python classesAndreas Hansson
2012-02-12mem: fix cache stats to use request ids correctlyDam Sunwoo
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-12prefetcher: Make prefetcher a sim object instead of it being a parameter on c...Mrinmoy Ghosh
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-31MEM: Remove the otherPort from the cache portsAndreas Hansson
2012-01-28Merge with the main repo.Gabe Black
2012-01-17MEM: Remove the functional ports from the memory systemWilliam Wang
2012-01-17MEM: Separate queries for snooping and address rangesAndreas Hansson
2012-01-17MEM: Remove Port removeConn and MemObject deletePortRefsAndreas Hansson
2012-01-17MEM: Simplify ports by removing EventManagerAndreas Hansson
2012-01-17MEM: Differentiate functional cache accesses from CPU and memoryAndreas Hansson
2012-01-07Merge with main repository.Gabe Black
2011-11-18SE/FS: Get rid of includes of config/full_system.hh.Gabe Black
2011-11-07SE/FS: Get rid of FULL_SYSTEM in mem.Gabe Black
2011-10-31GCC: Get everything working with gcc 4.6.1.Gabe Black
2011-09-13Prefetch: Don't prefetch if address is in the write queue.Ali Saidi
2011-09-01Fix build for gcc-4.2 opt/fastLisa Hsu
2011-08-19Mem: Put prefetcher notify call before packet is deleted.Ali Saidi
2011-08-19Prefetcher: Fix some memory leaks with the prefetcher.Ali Saidi
2011-07-15Mem: Fix issue with prefetches originating at non-L1 caches getting stale dataAli Saidi
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-04-19stats: rename stats so they can be used as python expressionsNathan Binkert
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-02-23Includes: Don't include isa_traits.hh and use the TheISA namespace unless rea...Ali Saidi
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-11-19SCons: Support building without an ISAAli Saidi
2010-10-18cache: minor SC assertion fixSteve Reinhardt
2010-10-13Mem: Change the CLREX flag to CLEAR_LL.Gabe Black
2010-09-21cache: improve coherence handling of writebacksSteve Reinhardt
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