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path: root/src/mem/cache
AgeCommit message (Expand)Author
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-07-03mem: Delay responses in the crossbar before forwardingAndreas Hansson
2015-07-03mem: Remove redundant is_top_level cache parameterAndreas Hansson
2015-07-03mem: Split WriteInvalidateReq into write and invalidateAndreas Hansson
2015-07-03mem: Add ReadCleanReq and ReadSharedReq packetsAndreas Hansson
2015-07-03mem: Allow read-only caches and check complianceAndreas Hansson
2015-07-03mem: Add clean evicts to improve snoop filter trackingAli Jafri
2015-06-09mem: Fix snoop packet data allocation bugAndreas Hansson
2015-03-17mem: Create a request copy for deferred snoopsStephan Diestelhorst
2015-05-05mem: Snoop into caches on uncacheable accessesAndreas Hansson
2015-05-05mem: Pass shared downstream through cachesAndreas Hansson
2015-05-05mem: Add forward snoop check for HardPFReqsAli Jafri
2015-05-05mem: Add missing stats update for uncacheable MSHRsAndreas Hansson
2015-05-05mem: Tidy up BaseCache parametersAndreas Hansson
2015-05-05mem: Remove templates in cache modelDavid Guillen
2015-03-27mem: Support any number of master-IDs in stride prefetcherStephan Diestelhorst
2015-03-27mem: Allocate cache writebacks before new MSHRsAndreas Hansson
2015-03-27mem: Cleanup flow for uncacheable accessesAndreas Hansson
2015-03-27mem: Ignore uncacheable MSHRs when finding matchesAndreas Hansson
2015-03-27mem: Remove redundant allocateUncachedReadBuffer in cacheAndreas Hansson
2015-03-27mem: Modernise MSHR iterators to C++11Andreas Hansson
2015-03-27mem: Align all MSHR entries to block boundariesAndreas Hansson
2015-03-27mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHEDAli Jafri
2015-03-19mem: Use emplace front/back for deferred packetsAndreas Hansson
2015-02-11mem: remove redundant test in in Cache::recvTimingResp()Steve Reinhardt
2015-02-11mem: add local var in Cache::recvTimingResp()Steve Reinhardt
2015-03-14mem: clean up write buffer check in Cache::handleSnoop()Steve Reinhardt
2015-03-02mem: Unify all cache DPRINTF address formattingAndreas Hansson
2015-03-02mem: Fix cache MSHR conflict determinationAndreas Hansson
2015-03-02mem: Add option to force in-order insertion in PacketQueueStephan Diestelhorst
2015-03-02mem: Downstream components consumes new crossbar delaysMarco Balboni
2015-03-02mem: Tidy up the cache debug messagesAndreas Hansson
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-03-02mem: Fix prefetchSquash + memInhibitAsserted bugAli Jafri
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2015-02-11mem: Clarify usage of latency in the cacheMarco Balboni
2015-02-03mem: Clarify express snoop behaviourAndreas Hansson
2015-02-03mem: Clarify cache behaviour for pending dirty responsesAndreas Hansson
2015-01-22mem: Remove Packet source from ForwardResponseRecordAndreas Hansson
2015-01-20mem: Fix bug in cache request retry mechanismAndreas Hansson
2014-12-23mem: Change prefetcher to use random_mtMitch Hayenga
2014-12-23mem: Hide WriteInvalidate requests from prefetchersCurtis Dunham
2014-12-23mem: Fix event scheduling issue for prefetchesMitch Hayenga
2014-12-23mem: Fix bug relating to writebacks and prefetchesMitch Hayenga
2014-12-23mem: Rework the structuring of the prefetchersMitch Hayenga
2014-12-23mem: Add parameter to reserve MSHR entries for demand accessMitch Hayenga
2014-12-02mem: Support WriteInvalidate (again)Curtis Dunham
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