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2018-11-13mem-cache: Align how we handle requests in atomic with timingNikos Nikoleris
Requests, for which a cache has already committed to respond do not perform any lookups. Previously in atomic mode the packet would pay the lookup latency while in timing it wouldn't. This patch aligns recvAtomic with recvTimingReq and removes the lookup latency from the the handling of such requests. Change-Id: I50a0631f8058e5086d94d55af0e1788a60e2883f Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/14175 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2018-11-05mem-cache: Rename the tag class init function to tagsInit.Gabe Black
Since the tag classes are subclasses of SimObject, they inherit an init function which does generic initialization at simulation startup and which doesn't take any parameters. A new function was added which does take a parameter, and which is just for doing tag specific initialization as triggered by the base cache. These two names clashed, and clang complained that the tag local name was hiding the SimObject name (which it was). Change-Id: I399775aceaf8f1a8e2646d434facef22e6d3e7d0 Reviewed-on: https://gem5-review.googlesource.com/c/13875 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-05mem: Use Packet writing functions instead of memcpyDaniel R. Carvalho
Classes were using memcpy instead of the Packet functions created for writing to/from the packet. This allows these writes to be better checked and tracked. This also fixes a bug in MemCheckerMonitor, which was using the incorrect type for the packet pointer. Change-Id: I5bbc8a24e59464e8219bb6d54af8209e6d4ee1af Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13695 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-11-05mem-cache: Fix double block invalidationDaniel R. Carvalho
Block was being invalidated twice when not a tempBlock. Make explicit that the else case is only to be applied when handling the tempBlock, as otherwise the Tags should be taking care of the invalidation. Change-Id: Ie7603fdbe156c54e94bbdc83541b55e66f8d250f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13895 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-26arch-arm: We add PRFM PST instruction for armyuetsu.kodama
Note current PRFM supports only PLD, but PST (prefetch for store) is also important for latency hiding. We also bug fix in disassembler to display prfop correctly. Change-Id: I9144e7233900aa2d555e1c1a6a2c2e41d837aa13 Signed-off-by: Yuetsu Kodama <yuetsu.kodama@riken.jp> Reviewed-on: https://gem5-review.googlesource.com/c/13675 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-22mem-cache: Move evictBlock(CacheBlk*, PacketList&) to baseDaniel R. Carvalho
Move evictBlock(CacheBlk*, PacketList&) to base cache, as it is both sub-classes implementations are equal. Change-Id: I80fbd16813bfcc4938fb01ed76abe29b3f8b3018 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13656 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem-cache: Fix unused variable warning in FALRU:invalidate()Nikos Nikoleris
Change-Id: I3b902045433ca56b3e62c251158e784b5fa9e4d7 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13600 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2018-10-18mem: Add write coalescing and write-no-allocate to the cachesNikos Nikoleris
Enable the cache to detect contiguous writes and hold on to the MSHR long enough to allow the entire line to be written. If the whole line is written, the MSHR will be sent out as an invalidation requests, as it is part of a whole-line write, i.e. no-fetch-on-write. The cache is also able to switch to a write-no-allocate policy on the actual completion of the writes, and instead use the tempBlock and turn the write operation into a writeback. These policies are all well-known, and described in works such as Jouppi, Cache Write Policies and Performance, vol 21, no 2, ACM, 1993. Change-Id: I19792f2970b3c6798c9b2b493acdd156897284ae Reviewed-on: https://gem5-review.googlesource.com/c/12907 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Delay servicing an MSHR after its allocationNikos Nikoleris
An MSHR is allocated and the computed latency determines when the MSHR will be ready and can be serviced by the cache. This patch adds a function that allows changing the time that an MSHR is ready and adjusts the queue such that other MSHRs can be serviced first if they are ready. Change-Id: Ie908191fcb3c2d84d4c6f855c8b1e41ca5881bff Reviewed-on: https://gem5-review.googlesource.com/c/12906 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Restructure whole-line writes to simplify write mergingNikos Nikoleris
This patch changes how we deal with whole-line writes their responses. With these changes, we use the MSHR tracking to determine if a whole-line is written, and on a fill we simply handle the invalidation response, with the actual writes taking place as part of satisfying the CPU-side hit. Change-Id: I9a18e41a95db3c20b97f8bca7d95ff33d35a578b Reviewed-on: https://gem5-review.googlesource.com/c/12905 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-18mem: Determine if an MSHR does a whole-line writeNikos Nikoleris
This patch adds support for determining whether the targets in an MSHR are 1) only writes and 2) whether these writes are effectively a whole-line write. This patch adds the necessary functions in the MSHR to allow for write coalescing in the cache. Change-Id: I2c9a9a83d2d9b506a491ba5b0b9ac1054bdb31b4 Reviewed-on: https://gem5-review.googlesource.com/c/12904 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-13mem-cache: Add missing includes in TreePLRUDaniel
Add missing includes to TreePLRU files. Change-Id: Ia1e7b2aa91eec8a30b6dccf513cca37a3058b350 Reviewed-on: https://gem5-review.googlesource.com/c/13477 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-11mem-cache: Factor ReplaceableEntry outDaniel R. Carvalho
ReplaceableEntry is referenced by many classes that do not necessarily need access to the replacement policies. Therefore, in order to allow better compilation units, we factor it out to a new file. Change-Id: I0823567bf1ca336ffcdf783682ef473e8878d7fd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13418 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-11mem-cache: Move sector_blks to tags folderDaniel R. Carvalho
Move sector_blks.hh and sector_blks.cc to the tags folder, as its usage scope is restricted to the tags, and caches should not be aware of them. Change-Id: Ia7a71f51ec251d827872daf108c87da543a0ba57 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13417 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-11mem-cache: Rename blk.cc/hh to cache_blk.cc/hhDaniel R. Carvalho
Rename the files blk.cc and blk.hh to cache_blk.cc and cache_blk.hh to comply with the usual file-class naming rules. Change-Id: I8af45df3e4b8dd934fd9929ec914fb230cb2cb09 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13416 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-11mem-cache: Virtualize block printDaniel R. Carvalho
Encapsulate and virtualize block print, so that relevant information can be easily printed anywhere. Change-Id: I91109c29c126755183a0fd2b4446f5335e64076b Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13415 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-10mem-cache: Create Tree-PLRU replacement policyDaniel R. Carvalho
Implementation of a Tree-PLRU replacement policy. It is based on the assumption that a set associative cache is used. Change-Id: I74b227e88fd6c93aab5bb2cd0e8730376db28f52 Reviewed-on: https://gem5-review.googlesource.com/c/11106 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Remove CacheSet.hhDaniel R. Carvalho
Replacement policies aren't aware of cache sets and do not organize blocks based on replacement data. Block search is independent of block placement. Besides, indexing policies have their own way of addressing the sets, therefore there is no need to use this class anymore. BlkType has been removed, as it wasn't being used. Change-Id: Ia79c2a491e59f295c8d60a0466c317eb0e2bdab9 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/9782 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-10mem-cache: Split Tags for indexing policiesDaniel R. Carvalho
Split indexing functionality from tags, so that code duplication is reduced when adding new classes that use different indexing policies, such as set associative, skewed associative or other hash-based policies. An indexing policy defines the mapping between an address' set and its physical location. For example, a conventional set assoc cache maps an address to all ways in a set using an immutable function, that is, a set x is always mapped to set x. However, skewed assoc caches map an address to a different set for each way, using a skewing function. FALRU has been left unmodified as it is a specialization with its own complexity. Change-Id: I0838b41663f21eba0aeab7aeb7839e3703ca3324 Reviewed-on: https://gem5-review.googlesource.com/c/8885 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Use set and way for ReplaceableEntryDaniel R. Carvalho
Replaceable entries belong to table-like structures, and therefore they should be indexable by combining a row and a column. These, using conventional cache nomenclature translate to sets and ways. Make these entries aware of their sets and ways. The idea is to make indexing policies usable by other table-like structures. In order to do so we move sets and ways to ReplaceableEntry, which will be the common base among table entries. Change-Id: If0e3dacf9ea2f523af9cface067469ccecf82648 Reviewed-on: https://gem5-review.googlesource.com/c/12764 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Use possible locations to find blockDaniel R. Carvalho
Use possible locations to find block to make it placement policy independent. Change-Id: I4c9d9e1e1ff91ce12e85ca1970f927d8f4f5a93b Reviewed-on: https://gem5-review.googlesource.com/c/8884 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Create tags initialization functionDaniel R. Carvalho
Having the blocks initialized in the constructor makes it harder to apply inheritance in the tags classes. This patch decouples the block initialization functionality from the constructor by using an init() function. It also sets the parent cache. Change-Id: I0da7fdaae492b1177c7cc3bda8639f79921fbbeb Reviewed-on: https://gem5-review.googlesource.com/c/11509 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-10mem-cache: Remove Packet dependency in TagsDaniel R. Carvalho
Decouple Tags from Packets, only extracting the necessary functionality for block insertion. As a side effect, create a new function to update common insertion statistics. Change-Id: I5c58f7c17de3255beee531f72a3fd25a30d74c90 Reviewed-on: https://gem5-review.googlesource.com/c/11098 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-05mem-cache: Fix FALRU hash invalidationDaniel R. Carvalho
The block was being invalidated before the hash could erase its entry, therefore it was using invalid values (tag was being assigned MaxAddr and the secure bit was reset). This change reorders the calls, so that the appropriate hash entry is erased. Change-Id: I161463df0f8f5220179bc68d7be12051e5390d01 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13210 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-05mem-cache: Make checking function const in FALRUDaniel R. Carvalho
The checking function should not be able to modify either the head and tail pointers nor should it modify its class. Change-Id: I2ad495f0c8c6b778d48512143e94b4c9a353f22e Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13209 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-10-05mem-cache: Make boundaries in FALRU an STL containerDaniel R. Carvalho
Turn the dynamically allocated array of pointers "boundaries" into a STL vector. Change-Id: I3409898473b155f69b4c6e038eba2dffb5b09380 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13208 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-05mem-cache: Fix FALRU inCachesMask initializationDaniel R. Carvalho
inCachesMask is not being initialized, which triggers an assertion on insertion. Fix this by implementing a default constructor for the FALRUBlk. Change-Id: I587cf5e0191c4587d938e6ab6036ec1b32f37793 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/13207 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-09-19mem-cache: Fix non-bijective function in Skewed cachesDaniel R. Carvalho
The hash() function must be bijective for the skewed caches to work, however when the hashing is done on top of a one-bit address, the MSB and LSB refer to the same bit, and therefore their xor will always be zero. This patch adds a fatal error to not allow the user to set an invalid value for the number of sets that would generate that bug. As a side note, the missing header for the bitfields functions has been added. Change-Id: I35a03ac5fdc4debb091f7f2db5db33568d0b0021 Reviewed-on: https://gem5-review.googlesource.com/12724 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-13mem-cache: Fix bug in handleAtomicReqMissNikos Nikoleris
"4976ff5 mem-cache: Refactor the recvAtomic function" introduced a bug where if an atomic request that fills in using the tempBlock it will not evict it when it finishes handling the request as it should. This triggers an assertion. This change fixes this bug. Change-Id: I73c808a7e15237eddb36b5448ef6728f7bcf7fd9 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12644 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-09-07mem-cache: Create Skewed Assoc placement policyDaniel R. Carvalho
Create a class that implements the skewed associative placement policy. It uses the hash function and expansions of the skewing functions described in "Skewed-Associative caches", by Seznec. Only 8 skewing functions are implemented, and therefore if more are needed a hash function will be recursively applied on top of the output of one of these functions to generate different values. This is not optimal, and if more functions are needed it might be more effective to implement them. Change-Id: Ibc77edffd8128114a8b200cec5d8deedfb5105cb Reviewed-on: https://gem5-review.googlesource.com/8886 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-07-25mem-cache: TempCacheBlk allocates and destroys its own dataRobert Kovacsics
This change is because I want to make CacheBlk::data private, so that I can track all the places which write to it. But to keep that commit smaller (it is pretty big, because of all the places which might change it), I have split this into a commit of its own. Change-Id: I15a2fc1752085ff3681f5c74ec90be3828a559ea Reviewed-on: https://gem5-review.googlesource.com/11829 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-07-23mem: Rename Packet::checkFunctional to trySatisfyFunctionalRobert Kovacsics
Packet::checkFunctional also wrote data to/from the packet depending on if it was read/write, respectively, which the 'check' in the name would suggest otherwise. This renames it to doFunctional, which is more suggestive. It also renames any function called checkFunctional which calls Packet::checkFunctional. These are - Bridge::BridgeMasterPort::checkFunctional - calls Packet::checkFunctional - MSHR::checkFunctional - calls Packet::checkFunctional - MSHR::TargetList::checkFunctional - calls Packet::checkFunctional - Queue<>::checkFunctional (of src/mem/cache/queue.hh, not src/cpu/minor/buffers.h) - Instantiated with Queue<WriteQueueEntry> and Queue<MSHR> - WriteQueueEntry - calls Packet::checkFunctional - WriteQueueEntry::TargetList - calls Packet::checkFunctional - MemDelay::checkFunctional - calls QueuedSlavePort/QueuedMasterPort::checkFunctional - Packet::checkFunctional - PacketQueue::checkFunctional - calls Packet::checkFunctional - QueuedSlavePort::checkFunctional - calls PacketQueue::doFunctional - QueuedMasterPort::checkFunctional - calls PacketQueue::doFunctional - SerialLink::SerialLinkMasterPort::checkFunctional - calls Packet::doFunctional Change-Id: Ieca2579c020c329040da053ba8e25820801b62c5 Reviewed-on: https://gem5-review.googlesource.com/11810 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-07-19mem-cache: Typo in comment: 'proceed' -> 'precede'Robert Kovacsics
The writebacks happen before anything below, not after. Change-Id: I7eaefbbf33aa17c496255dedd964a56118a28741 Reviewed-on: https://gem5-review.googlesource.com/11749 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-22mem-cache: Promote deferred targets on cache clean responsesNikos Nikoleris
While a cache clean operation is pending, all requests to the corresponding block get deferred. When the response of a cache clean operation is received, if the block is present and the response is not invalidating, we can service all deferred targets that didn't require writable. This change implements this functionality. Change-Id: Ief47e74d07749a6a9736ab450eb46eefa53464a2 Reviewed-on: https://gem5-review.googlesource.com/11018 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-22mem-cache: Promote targets that don't require writableNikos Nikoleris
Until now, all deferred targets of an MSHR would be promoted together as soon as the targets were serviced. Due to the way we handle cache clean operations we might need to promote only deferred targets that don't require writable, leaving some targets as deferred. This change adds support for this selective promotion. Change-Id: I502e523dc9adbaf394955cbacea8286ab6a9b6bc Reviewed-on: https://gem5-review.googlesource.com/11017 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-22mem-cache: Fix promoting of targets that need writableNikos Nikoleris
There are cases where a request which does not need a writable copy gets an response upgraded reponse and fills in a writable copy. When this happens, we promote deferred MSHR targets that were deferred because they needed a writable copy to service them immediately. Previously, we would uncoditionally promote deferred targets. Since the deferred targets might contain a cache invalidation operation, we have to make sure that any targets following the cache invalidation is not promoted. Change-Id: I1f7b28f7d35f84329e065c8f63117db21852365a Reviewed-on: https://gem5-review.googlesource.com/11016 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-22mem-cache: Selectively clear downstream pendingNikos Nikoleris
Until now, all deferred targets of an MSHR would be promoted together as soon as the targets were serviced. When we promote deferred targets we also clear the downstreamPending flag. Due to the way we handle cache clean operations we might need to promote only deferred targets that don't require writable, leaving some targets as deferred. To allow for partial target promotion, this change adds support for clearing the downstreamPending only for a subset of a TargetsList. Change-Id: Id06953643ba9a975ebacc76ac10215441e264e74 Reviewed-on: https://gem5-review.googlesource.com/11015 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-06-20mem-cache: Fix TempCacheBlock insertJason Lowe-Power
TempCacheBlock insert() had a different signature than the parent class which caused an error on clang. This matches the signature with default zero values. Change-Id: Ic096914497f3d17e88295c9e65a04d76fdddf365 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/11349 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-19mem-cache: Fix support for secure blocks in the FALRU cacheNikos Nikoleris
Fully associative caches use an unordered map to enable efficient lookups of existing blocks. Previously this map was indexed using the tag of the block. Security extentions allow secure and non secure versions of a block with the same tag to co-exist in the cache. This patch amends the block map to allow correct lookups for FALRU caches. Change-Id: Iccf07464deab56d1d270bae14bb3b154047e3556 Reviewed-on: https://gem5-review.googlesource.com/11309 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-15mem-cache: Initialize CacheBlk data pointerDaniel R. Carvalho
Initialize CacheBlk's data pointer as a nullptr. Change-Id: Ice85b4b11495cad4b0a160ccb9efe1be673e57e2 Reviewed-on: https://gem5-review.googlesource.com/11097 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-15mem-cache: Forward declare ReplaceableEntryDaniel R. Carvalho
Forward declare ReplaceableEntry where in classes where pointers to it are used. Change-Id: I49c08d36442a563d7a6b4c9bcd7eba3591d29b60 Reviewed-on: https://gem5-review.googlesource.com/11096 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-14base,mem: Support AtomicOpFunctor in the classic memory systemTuan Ta
AtomicOpFunctor can be used to implement atomic memory operations. AtomicOpFunctor is captured inside a memory request and executed directly in the memory hierarchy in a single step. This patch enables AtomicOpFunctor pointers to be included in a memory request and executed in a single step in the classic cache system. This patch also makes the copy constructor of Request class do a deep copy of AtomicOpFunctor object. This prevents a copy of a Request object from accessing a deleted AtomicOpFunctor object. Change-Id: I6649532b37f711e55f4552ad26893efeb300dd37 Reviewed-on: https://gem5-review.googlesource.com/8185 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-13mem-cache: Remove unnecessary cast in SectorTags::findVictimNikos Nikoleris
Removes an uneccessary cast that also caused an unused variable error (due to -Werror) when compiling .fast targets. Change-Id: Ic043f462925e7eaa7b691455f1d9e08a1c101980 Reviewed-on: https://gem5-review.googlesource.com/11119 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-13mem-cache: Insert on block allocationDaniel R. Carvalho
When a block is being replaced in an allocation, if successfull, the block will be inserted. Therefore we move the insertion functionality to allocateBlock(). allocateBlock's signature has been modified to allow this modification. Change-Id: I60d17a83ff4f3021fdc976378868ccde6c7507bc Reviewed-on: https://gem5-review.googlesource.com/10812 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-13mem-cache: Make packet const in insertBlockDaniel R. Carvalho
The packet should not be modified within insertBlock. Change-Id: If7d2b01fe131f9923194efd155c9e85eeab24d5a Reviewed-on: https://gem5-review.googlesource.com/10811 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-13mem-cache: Create Sector CacheDaniel R. Carvalho
Implementation of Sector Caches, i.e., a cache with multiple sequential data entries per tag entry for Set Associtive placement policies. Change-Id: I8e1e9448fa44ba308ccb16cd5bcc5fd36c988feb Reviewed-on: https://gem5-review.googlesource.com/9741 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
Every usage of Request* in the code has been replaced with the RequestPtr alias. This is a preparing patch for when RequestPtr will be the typdefed to a smart pointer to Request rather then a raw pointer to Request. Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10995 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-06-08mem-cache: Change Cache block tag checkDaniel R. Carvalho
Change tag to address check for compatibility with sector design. Cache should not use tag, as sector sub-blocks share them, and it could lead to wrong accesses. Change-Id: Id1fa26f417595f475c5b5c07ae1f02f5fa0684ba Reviewed-on: https://gem5-review.googlesource.com/10723 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-08mem-cache: Use secure bit in findVictimDaniel R. Carvalho
Sector caches must know if there was a sector hit in order to decide whether a victim's sector must be fully evicted to give place to a new sector or not. In order to do so it needs the tag and secure information. Change-Id: Ib554169e25fa131d6bf986561f7970b787c56874 Reviewed-on: https://gem5-review.googlesource.com/10722 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-12 03:04:45 +0000