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2006-10-19Always get the functional access from the highest level of cache first.Ron Dreslinski
src/mem/cache/cache_impl.hh: Get the read data from the highest level of cache on a functional access --HG-- extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
2006-10-18Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : 9e47881686a6c060fa28e7edfd9a0b556099bf30
2006-10-18Break a lot of overly long lines.Steve Reinhardt
Factor out some asserts that were on both sides of an if/else. --HG-- extra : convert_revision : 78f0c2d76a81a98216b2f281159c6b6ea0147731
2006-10-18Get rid of doData() lines (were already commented out).Steve Reinhardt
Reindent due to resulting changes in nesting. --HG-- extra : convert_revision : 6be099d572efb618efb08fbc06d7e0e4b5b4cab2
2006-10-18Get rid of obsolete in-cache copy support.Steve Reinhardt
--HG-- extra : convert_revision : a701ed9d078c67718a33f4284c0403a8aaac7b25
2006-10-17Include packet_impl.hh (need this on my laptop,Steve Reinhardt
but not on zizzer... g++ 4 thing maybe?) --HG-- extra : convert_revision : 31c49f1c55fe9daf6365411bfb5bb7f6ccc8032d
2006-10-17Fixes for uni-coherence in timing mode for FS.Ron Dreslinski
Still a bug in atomic uni-coherence in FS. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Make CPU models handle coherence requests src/mem/cache/base_cache.cc: Properly signal coherence CSHRs src/mem/cache/coherence/uni_coherence.cc: Only deallocate once --HG-- extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
2006-10-17Fixes to cache eliminating the assumption that the Packet is still valid ↵Ron Dreslinski
after sending out a request. Still need to rework upgrades into this system, but works for now. src/mem/cache/base_cache.cc: Re order code to be more readable src/mem/cache/base_cache.hh: Be sure to delete the copy on a bus block src/mem/cache/cache_impl.hh: Be sure to remove the copy on a writeback success src/mem/cache/miss/mshr_queue.cc: Demorgans to make it easier to understand src/mem/tport.cc: Delete writebacks --HG-- extra : convert_revision : 9519fb37b46ead781d340de29bb342a322a6a92e
2006-10-17Properly chack the pkt pointer on upgrades to insure no segfaults when ↵Ron Dreslinski
writebacks delete the packet. --HG-- extra : convert_revision : 72b1c6296a16319f4d16c62bc7038365654dbc40
2006-10-17Fix it so that the cache does not assume to gave the packet it sent out via ↵Ron Dreslinski
sendTiming. Still need to fix upgrades to use this path src/mem/cache/base_cache.cc: Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed src/mem/cache/cache_impl.hh: Use copy of packet, because sendTiming may have changed the pkt Also, delete the copy when the time comes --HG-- extra : convert_revision : 635cde6b4f08d010affde310c46b1caf50fbe424
2006-10-17Merge zizzer:/bk/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : c3650273684f3fbdcd2e14e95d09ee3c6de8d6b6
2006-10-14Get rid of unused CacheBlk << output operator.Steve Reinhardt
--HG-- extra : convert_revision : d5c0aadc35edf5c9495afcd3375f1f64716ef845
2006-10-13Fix for DMA's in FS caches.Ron Dreslinski
Fix CSHR's for flow control. Fix for Bus Bridges reusing packets (clean flags up) Now both timing/atomic caches with MOESI in UP fail at same point. src/dev/io_device.hh: DMA's should send WriteInvalidates src/mem/bridge.cc: Reusing packet, clean flags in the packet set by bus. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Fix CSHR's for flow control. src/mem/packet.hh: Make a writeInvalidateResp, since the DMA expects responses to it's writes --HG-- extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
2006-10-12Fix CSHR retrysRon Dreslinski
--HG-- extra : convert_revision : caa7664f6c945396fa38ce62fbda018ebed4eaa6
2006-10-12Remove bus and top level parameters from cacheRon Dreslinski
src/mem/cache/base_cache.hh: Remove top level param from cache src/mem/cache/coherence/uni_coherence.cc: Remove top level parameters from the cache --HG-- extra : convert_revision : 4437aeedc20866869de7f9ab123dfa7baeebedf0
2006-10-12Check the response queue on functional accesses.Ron Dreslinski
The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses? src/mem/cache/base_cache.cc: src/mem/tport.cc: Add in functional check of retry queued packets. --HG-- extra : convert_revision : 0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
2006-10-12Fix problems with unCacheable addresses in timing-coherenceRon Dreslinski
src/base/traceflags.py: src/mem/physical.cc: Add debug falgs fro physical memory accesses src/mem/cache/cache_impl.hh: Snoops to uncacheable blocks should not happen src/mem/cache/miss/miss_queue.cc: Set the size properly on unCacheable accesses --HG-- extra : convert_revision : fc78192863afb11fc7c591fba169021b9e127d16
2006-10-11More cache fixes. Atomic coherence now works as well.Ron Dreslinski
src/cpu/memtest/memtest.cc: src/cpu/memtest/memtest.hh: Make Memtester able to test atomic as well src/mem/bus.cc: src/mem/bus.hh: Handle atomic snoops properly for cache->cache transfers src/mem/cache/cache_impl.hh: Debug output. Clean up memleak in atomic mode. Set hitLatency. Still need to send back reasonable number for atomic return value. src/mem/packet.cc: Add command strings for new commands src/python/m5/objects/MemTest.py: Add param to test atomic memory. --HG-- extra : convert_revision : 43f880e29215776167c16ea90793ebf8122c785b
2006-10-11Use bus response time paramteresRon Dreslinski
Fix bug with deadlocking src/mem/cache/base_cache.cc: Make sure to not wait anymore --HG-- extra : convert_revision : 5f7b44a1c475820b9862275a0d6113ec2991735d
2006-10-11When turning asserts into if's don't forget to invert.Ron Dreslinski
src/mem/cache/base_cache.cc: When turning asserts into if's don't forget to invert. Must be too sleepy. --HG-- extra : convert_revision : ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
2006-10-11Writebacks can be pulled out from under the BusRequest when snoops of ↵Ron Dreslinski
uprgades to owned blocks hit in the WB buffer --HG-- extra : convert_revision : f0502836a79ce303150daa7e571badb0bce3a97a
2006-10-10Only issue responses if we aren;t already blockedRon Dreslinski
--HG-- extra : convert_revision : 511c0bcd44b93d5499eefa8399f36ef8b6607311
2006-10-10Debugging infoRon Dreslinski
src/base/traceflags.py: Add new flags for cacheport src/mem/bus.cc: Add debugging info src/mem/cache/base_cache.cc: Add debuggin info --HG-- extra : convert_revision : a6c4b452466a8e0b50a86e886833cb6e29edc748
2006-10-10Some more code cleanupRon Dreslinski
src/mem/cache/base_cache.cc: Add sanity checks src/mem/cache/base_cache.hh: Fix for retry mechanism --HG-- extra : convert_revision : 9298e32e64194b1ef3fe51242595eaa56dcbbcfd
2006-10-10Fix some more mem leaks, still some leftRon Dreslinski
Update retry mechanism src/mem/cache/base_cache.cc: Rework the retry mechanism src/mem/cache/base_cache.hh: Rework the retry mechanism Try to fix memory bug src/mem/cache/cache_impl.hh: Rework upgrades to not be blocked by slave src/mem/cache/miss/mshr_queue.cc: Fix mem leak on writebacks --HG-- extra : convert_revision : 3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
2006-10-10Fix cshr Retry'sRon Dreslinski
Fix Upgrades being blocked by slave --HG-- extra : convert_revision : cca98a38e32233145163577500f1362cd807ab15
2006-10-10Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest src/mem/packet.hh: Hand merge code --HG-- extra : convert_revision : d659418f24f4f4bf9867fec8573a5d227c0dfcea
2006-10-10Fix several bugs pertaining to upgrades/mem leaks.Ron Dreslinski
src/mem/cache/base_cache.cc: Fix a bug about not having a request to send src/mem/cache/base_cache.hh: Fix a bug with the blocking code src/mem/cache/cache.hh: AFix a bug with snoop hits in WB buffer src/mem/cache/cache_impl.hh: Fix a bug with snoop hits in WB buffer Also, add better DPRINTF's src/mem/cache/miss/miss_queue.cc: Fix a bug with upgrades (Need to clean it up later) src/mem/cache/miss/mshr.cc: Fix a memory leak bug, still some outstanding with writebacks not being deleted src/mem/cache/miss/mshr_queue.cc: Fix a bug about upgrades (need to clean up later) src/mem/packet.hh: Fix for newly added cmd attribute for upgrades tests/configs/memtest.py: More interesting testcase --HG-- extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
2006-10-09Handle NACK's that occur from devices on the same bus.Ron Dreslinski
Not fully implemented yet, but good enough for single level cache coherence src/mem/packet.hh: Add a bit to distinguish invalidates and upgrades --HG-- extra : convert_revision : 5bf50d535857cea37fbdaf7993915d1332cb757e
2006-10-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus --HG-- extra : convert_revision : 2adde42edead2cedeeba60cc0d2697a2d58682be
2006-10-09Fix how upgrades work.Ron Dreslinski
Remove some dead code. src/mem/cache/cache_impl.hh: Upgrades don't need a response. Moved satisfied check into bus so removed some dead code. src/mem/cache/coherence/coherence_protocol.cc: src/mem/packet.hh: Upgrades don't require a response --HG-- extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
2006-10-09One step closet to having NACK's work.Ron Dreslinski
src/cpu/memtest/memtest.cc: Fix functional return path src/cpu/memtest/memtest.hh: Add snoop ranges in src/mem/cache/base_cache.cc: Properly signal NACKED src/mem/cache/cache_impl.hh: Catch nacked packet and panic for now --HG-- extra : convert_revision : 59a64e82254dfa206681c5f987e6939167754d67
2006-10-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus --HG-- extra : convert_revision : 8267487b935eaf11665841ace3a5c664751b53b0
2006-10-09Fix a typo in the printfRon Dreslinski
--HG-- extra : convert_revision : bfa8ffae0a9bef25ceca168ff376ba816abf23f3
2006-10-09Fix a bitwise operation that was accidentally a logical operation.Ron Dreslinski
--HG-- extra : convert_revision : 30f64bcb6bea47fd8cd6d77b0df17eff04dbbad0
2006-10-09Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : b4cb1702ffa2fca298cfde47683cac019e1da900
2006-10-09Add more DPRINTF's fix a supply condition.Ron Dreslinski
src/mem/cache/cache_impl.hh: Add more usefull DPRINTF's REmove the PC to get rid of asserts --HG-- extra : convert_revision : 3f6d832b138d058dbe79bb5f42bd2db9c50b35b5
2006-10-09Set size properly on uncache accessesRon Dreslinski
Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/blocking_buffer.hh: src/mem/cache/miss/miss_queue.hh: Don't use the senderState after you get a succesful sendTiming. Not guarnteed to be correct --HG-- extra : convert_revision : 2e8e812bf7fd3ba2b4cba7f7173cb41862f761af
2006-10-09Have cpus send snoop rangesRon Dreslinski
--HG-- extra : convert_revision : 2a1fba141e409ee1d7a0b69b5b21d236e3d4ce68
2006-10-09Don't create a response if one isn't needed.Ron Dreslinski
--HG-- extra : convert_revision : 37bd230f527f64eb12779157869aae9dcfdde7fd
2006-10-09Don't block responses even if the cache is blocked.Ron Dreslinski
--HG-- extra : convert_revision : a1558eb55806b2a3e7e63249601df2c143e2235d
2006-10-08Make sure to propogate sendFunctional calls with functional not atomic.Ron Dreslinski
src/mem/cache/cache_impl.hh: Fix a error case by putting a panic in. Make sure to propogate sendFunctional calls with functional not atomic. --HG-- extra : convert_revision : 05d03f729a40cfa3ecb68bcba172eb560b24e897
2006-10-08Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus src/mem/bus.cc: Hand merged. Needs to be fixed --HG-- extra : convert_revision : df03219ccfd18431cc726a063bd29d30554944a1
2006-10-08Only respond if the pkt needs a response.Ron Dreslinski
Fix an issue with memory handling writebacks. src/mem/cache/base_cache.hh: src/mem/tport.cc: Only respond if the pkt needs a response. src/mem/physical.cc: Make physical memory respond to writebacks, set satisfied for invalidates/upgrades. --HG-- extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd
2006-10-08Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest --HG-- extra : convert_revision : f3067efb7f3ff30158d541dfc52de4ea8edae576
2006-10-08Move away from using the statusChange function on snoops. Clean up snooping ↵Ron Dreslinski
code in general. --HG-- extra : convert_revision : 5a57bfd7742a212047fc32e8cae0dc602fdc915c
2006-10-08missing elseGabe Black
--HG-- extra : convert_revision : 8fe0e00dc3ae70b4449a78c15dd249939e644f02
2006-10-08Replace tests of LOCKED/UNCACHEABLE flags with isLocked()/isUncacheable().Steve Reinhardt
--HG-- extra : convert_revision : f22ce3221d270ecf8631d3dcaed05753accd5461
2006-10-07Fix a missing pointerRon Dreslinski
--HG-- extra : convert_revision : 2056b530d48fd004ab700f09e58f44adae3ea0e9
2006-10-07No need to keep trying to request the data bus if we are already waiting.Ron Dreslinski
--HG-- extra : convert_revision : dbaad52ed8d0841dc9224661e3df0d8ef4989aa3
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