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2020-01-17mem-cache: Add getter for the number of valid sub-blksDaniel R. Carvalho
Add a getter function so that the number of valid sub-blocks can be retrieved. As a side effect, make the respective counter private. Change-Id: Icef8b51164c8e165872dcaebc65f5c330f16cb29 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22605 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-17mem-cache: Add multiple eviction statsDaniel R. Carvalho
Add stats to inform how many blocks were evicted due to a sector replacement/eviction. Change-Id: I886365506016d0888f835d182b3b65a808a9dccd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22606 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-17mem-cache: Make findVictim non-constDaniel R. Carvalho
In order to acquire stats when a victim is found, findVictim must be made const. Change-Id: I493c7849f07625c90b2b95fd220f50751f4d0f52 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22604 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-17mem-cache: Add more compression statsDaniel R. Carvalho
Add stats to calculate the total number of compressions, decompressions and the average compression size, in number of bits. Change-Id: I5eb563856c1ff54216e1edcd2886332b7481cbfe Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22609 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-17mem-cache: Factor out multiple block evictionDaniel R. Carvalho
Create a function to try to evict multiple blocks while checking for transient state. Change-Id: I6a879fa5e793cd92c4bdf4a258a133de4c865012 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22607 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2020-01-07mem-cache: Forward snoops when the cache is not respondingNikos Nikoleris
When the MSHR is handling a request that will make the block dirty the current cache commits respond. When that's not the case the cache should forward any snoops. This CL fixes MSHR::handleSnoop() to implement this behavior. Change-Id: I207e3ca4968fd9528fd4cdbfb3eb95f470b4744d Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23668 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
2020-01-07mem-cache: Ensure that responses get data from the right sourceNikos Nikoleris
This CL makes sure that we use the right source for data for responses after a response from the cache below. Change-Id: I7329f3e6bcb7ce2054e912eb9dea48c9d169d45a Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23667 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-06mem-cache: Avoid write merging if there are reads in betweenNikos Nikoleris
This CL reworks the logic in the MSHR to make sure we do not coalesce requests unless there is a series of write requests for the whole cache block without any other incompatible requests (e.g., read) in between. Change-Id: I0b3195858fb33ef85d7aae27376506057dd53ea7 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23666 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-12mem-cache: Move unused prefetches counter updateDaniel R. Carvalho
The number of unused prefetches should be updated every time a block is invalidated, therefore we move the update to within the corresponding function. Change-Id: If3ac2ea43611525bd3c36d628d88382042fcb7dc Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18908 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-11-28mem-cache: Avoid hiding a virtual method in the dictionary compressor.Gabe Black
The non-virtual version is later used in overrides of the virtual version whcih takes more arguments. Change-Id: I102d1185c7a616337c2a0429daa998706189292f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23127 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-28mem-cache: Remove a std::move clang says is unnecessary.Gabe Black
It also says it prevents an optimization. Change-Id: I9c21dc1a0c53cf70cefd1400564de07d1e845a75 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23124 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18mem-cache: Initialize all members of `QueuedPrefetcher::DeferredPacket`.Isaac Sánchez Barrera
Members `tc` and `ongoingTranslation` were uninitialized in the constructor for `QueuedPrefetcher::DeferredPacket`. If `ongoingTranslation` is not initialized to `false` by default, some translation requests from queued prefetchers are not properly handled and executions are nondeterministic. Change-Id: Ia278f9e74847d6b847984d47f6a45643bae57794 Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22844 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18mem-cache: Fix destructor of `BasePrefetcher::PrefetchInfo`.Isaac Sánchez Barrera
The destructor of `BasePrefetcher::PrefetchInfo` was calling `delete` for a dynamically-allocated array. Changed to `delete[]` to remove potential undefined behaviour. Change-Id: I6f531bfb6fb7108f1d3e743ae0384d80173e15ef Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22843 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-04mem-cache: Modify compressor to appease newer compilersDaniel R. Carvalho
The type of the local unique_ptr variable was different from the return type. In C++11 because of such difference, a copy-ellision would not be possible, and that required the use of a std::move. In C++14 the restriction of same types being required was removed, so std::move would not be needed anymore. With the addition of the -Wredundant-move warning in newer compilers, having the std::move on the return became an issue, breaking compilation. Change-Id: I45d18dfc500bb5db5fe360814feb91853c735a19 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22403 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-11-04mem-cache: Implement a perfect compressorDaniel R. Carvalho
Implement a perfect compressor that always manages to compresses data exactly to its maximum allowed compression ratio. This allows tracking a compression upper bound. Change-Id: Ibc68bf2dc84b75207795d5ba6304b9ed6dbeae8f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21160 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Make BDI a multi compressorDaniel R. Carvalho
BDI is a compressor containing multiple sub-compressors. Change-Id: I98411e2ef9dcc2182801a172dfc59ed7a8ee7dd4 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21159 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a multi compressorDaniel R. Carvalho
Implement a compressor that contains multiple sub-compressors and choses the one that provides the best compression results for each compression. Change-Id: I758cf67c84bd85edbea16b2a07b2068b00454461 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21158 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-04mem-cache: Implement BDI sub-compressorsDaniel R. Carvalho
Implement sub-compressors of BDI as public compressors so that they can be used separately. Change-Id: I710e35f39f4abb82fd02fd33b1b86a3f214c12cb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21157 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a repeated values compressorDaniel R. Carvalho
The repeated values compressor can only compress data composed solely repeated instances of the same value. Change-Id: If2c4f47ad4af492d202ec2017e30ba52ee67e307 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21156 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement a zero compressorDaniel R. Carvalho
The zero compressor can only compress data composed solely of zero bits. Change-Id: I8b359c03776a8748abd144a178bda944b5a1b766 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21155 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-11-04mem-cache: Implement FPC-D cache compressionDaniel R. Carvalho
Implementation of Frequent Pattern Compression with limited Dictionary support (FPC-D) cache compressor, as described in "Opportunistic Compression for Direct-Mapped DRAM Caches", by Alameldeen et al. Change-Id: I26cc1646f95400b6a006f89754f6b2952f5b4aeb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21154 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-10-31mem-cache: Fix missing header in associative setDaniel R. Carvalho
Add missing intmath header to AssociativeSet, so that isPowerOf2 can be used. error: there are no arguments to 'isPowerOf2' that depend on a template parameter, so a declaration of 'isPowerOf2' must be available Change-Id: Ib2b194f9e71284ee439786bdb76d99858e57e2f5 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22444 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a repeated value pattern to compressorsDaniel R. Carvalho
The repeated value pattern checks if values are composed of multiple instances of the same value. If successful, the bits of the repeated value are included only once in the compressed data. Change-Id: Ia7045b4e33a91fd8d712fe1ca689f7f8cb4e5feb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21153 Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Inform unused bits instead of bytes in compressor patternDaniel R. Carvalho
Increase pattern precision by giving the number of unmatched bits instead of bytes. Change-Id: I5efbe9c31672cc973b4c89c741cdc8cc28d26285 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21152 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a masked const value pattern to compressorsDaniel R. Carvalho
The masked pattern compares values to masked const non-dictionary values to determine whether these match. If successful, the bits that do not match must be added to the compressed data. Change-Id: I4c53568694dab916136fe384cb2ee10e554f7136 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21151 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add a masked pattern to compressorsDaniel R. Carvalho
The masked pattern compares masked values to masked dictionary entries to determine whether these values match. If successful, the bits that do not match must be added to the compressed data. Change-Id: I4b1c8feb0faa99576382b54a73a20c353f965d2a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21150 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Add an uncompressed pattern to compressorsDaniel R. Carvalho
The uncompressed pattern always stores the original data, and therefore it is always successful. All of the derived classes of the dictionary compressor must have this pattern as the last pattern of the pattern factory. Change-Id: I2a38fd56630d88ef8b918220dc4c2824a196a8a2 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21149 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Templatize DictionaryCompressorDaniel R. Carvalho
Templatize DictionaryCompressor so that the dictionary entries' sizes can be changed. Change-Id: I3d89e3c692a721cefcd7e3c55d2ccdefa425f614 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21148 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Factor out CPack's dictionary functionalityDaniel R. Carvalho
Factor out dictionary functionality of CPack, so that it can be used easily for other compressors. As a side effect, create an addToDictionary function to allow subclasses to chose how to handle insertion. Change-Id: I02fae4e98b02db5a40467ec470b71020d5e867cb Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21147 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
2019-10-29mem-cache: Use shouldAllocate() instead of CPack's decompress()Daniel R. Carvalho
Split decompression functionality using the proper function to determine if a dictionary entry should be allocated after decompression or not. Change-Id: I4995304f4c4508c03c9fc1685f04511622969556 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21146 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Limit compression sizeDaniel R. Carvalho
Add a threshold so that if the compressed size is greater than it, the compression is abandoned, and the data is considered uncompressible. Change-Id: Ic416195b06ec440a40263b75bd0f0383cde2ea6a Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21144 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-10-29mem-cache: Do not try to compress dataless packetsDaniel R. Carvalho
Fix filling blocks so that packets that do not contain data do not generate a compression attempt. This can happen, for example, with invalidation responses, which will trigger a packet data access assertion. Change-Id: I2a1e7983657f6e5e770b148ab62c9de9ac3986ac Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22164 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-29mem-cache: Avoid promotion of incompatible deferred targetsNikos Nikoleris
Often a request that hits on an MSHR has to be deferred as it can't be serviced by the current response. For example, a request that requires writable has to be deferred when the response is expected to bring in a read-only copy of the block. However, there are cases where the response, although not expected to do so, brings a writable copy and as a result we also service deferred targets. In such cases, we promote deferred targets up until the first that can't be serviced by the current response (e.g., cache maintainance operation). If the first deferred target is incompatible we don't promote any targets at all. Change-Id: Ib3e13be51120b7c0f0053b83b76bde03e1b7dd4e Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22127 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-29mem-cache: Fix MSHR whole line write trackingNikos Nikoleris
The MSHR keeps track of outstanding writes and services them as a whole line write whenever possible. To do this the outstanding writes have to be compatible (e.g., not strictly ordered). Prior to this change, due to this tracking mechanism, the MSHR would not service a WriteLineReq with flags that do not allow merging as a full line write even if it was the first target triggering an assertion. This changeset fixes this bug. Change-Id: I2cbf5ece0c108c1fcfe6855e8f194408d5ab8ce2 Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22126 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-13mem-cache: set the second chance to false when inserting a blockMingyuan
Modify second chance replacement policy so that entries are inserted without a second chance. Previously, the second chance bit was set to true when a cache line was inserted. So the cache line would gain its second chance when inserting. This is wrong because the cache block will only get a second chance when it hits. Here's a quoted citation for the second chance replacement policy: "Whenever the algorithm examines a page entry, it extracts the associated usage bit and enters it into the high-order position of a k-bit shift register after shifting the contents of the register one bit-position lower. Then if the shift register is nonzero, the page is retained; if the shift register is zero, the page is replaced by the new page. In either case the usage bit for the page is turned off and the circular list pointer is advanced." (A Paging Experiment with the Multics System, FJ Corbato, 1968) Change-Id: I0d07e56aa16c67dd36e0d490c3f457f91e46f320 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20882 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-10-12mem-cache: Fixed a bug in MRU replacement policyMingyuan
The lastTouchTick is set to 0 when instantiate. This will cause the candidate[0] to get evicted over and over again in MRU replacement policy. To resolve this, break the search loop whenever it finds a cold cache line. Change-Id: I33aa57ebe0efca15986f62c3ae10a146bd2b779f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20881 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
2019-10-11mem-ruby: Allow Ruby to use all replacement policies in ClassicJingQuJQ
Add support in Ruby to use all replacement policies in Classic. Furthermore, if new replacement policies are added to the Classic system, the Ruby system will recognize new policies without any other changes in Ruby system. The following list all the major changes: * Make Ruby cache entries (AbstractCacheEntry) inherit from Classic cache entries (ReplaceableEntry). By doing this, replacement policies can use cache entries from Ruby caches. AccessPermission and print function are moved from AbstractEntry to AbstractCacheEntry, so AbstractEntry is no longer needed. * DirectoryMemory and all SLICC files are changed to use AbstractCacheEntry as their cache entry interface. So do the python files in mem/slicc/ast which check the entry interface. * "main='false'" argument is added to the protocol files where the DirectoryEntry is defined. This change helps differentiate DirectoryEntry from CacheEntry because they are both the instances of AbstractCacheEntry now. * Use BaseReplacementPolicy in Ruby caches instead of AbstractReplacementPolicy so that Ruby caches will recognize the replacement policies from Classic. * Add getLastAccess() and useOccupancy() function to Classic system so that Ruby caches can use them. Move lastTouchTick to ReplacementData struct because it's needed by getLastAccess() to return the correct value. * Add a 2-dimensional array of ReplacementData in Ruby caches to store information for different replacement policies. Note that, unlike Classic caches, where policy information is stored in cache entries, the policy information needs to be stored in a new 2-dimensional array. This is due to Ruby caches deleting the cache entry every time the corresponding cache line get evicted. Change-Id: Idff6fdd2102a552c103e9d5f31f779aae052943f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20879 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01mem-cache: Fix invalid whenReadyDaniel R. Carvalho
When a writeback needs to be allocated the whenReady field of the block is not set, and therefore its access latency calculation uses the previously invalidated value (MaxTick), significantly delaying execution. This is fixed by assuming that the data write portion of a write access is done regardless of previous writes, and that only the tag latency is important for the critical path latency calculation. Change-Id: I739132a2deab6eb4c46d084f4ee6dd65177873fd Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20068 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-09-30mem-cache: Switch to new-style statsAndreas Sandberg
This change puts cache and tag stats into a Stats::Group struct. This makes it easier to identify stat updates (they are prefixed with stat.) and adds hierarchy information for output formats that need it. Change-Id: I2b8e9138f1cb977abb445ec864d80a79b588481d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21140 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-12mem-cache: Fix BDI size calculationDaniel R. Carvalho
The bitmask field indicates to which base a delta refers, and in the original paper it is fixed and proportional to the highest number of bases allowed in the compressed data. Change-Id: I271bf2e19e0765de52b933eaf6d4fcc2ce25d185 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19748 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-29mem-cache: Use SatCounter for RRPVDaniel R. Carvalho
Use SatCounter in RRIP's RRPV. As such, move validation functionality to a proper variable. Change-Id: I142db2b7f6cd518ac3a2b68c9ed48005402b3464 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20452 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-28mem: Eliminate the Base(Slave|Master)Port classes.Gabe Black
The Port class has assumed all the duties of the less generic Base*Port classes, making them unnecessary. Since they don't add anything but make the code more complex, this change eliminates them. Change-Id: Ibb9c56def04465f353362595c1f1c5ac5083e5e9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20236 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-08-07mem-cache: Fix non-virtual base destructor of Repl EntryDaniel R. Carvalho
ReplaceableEntry contains a virtual method, yet its destructor was not virtual, causing errors in some compilers. Change-Id: I13deec843f4007d9deb924882a8d98ff6a89c84f Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19808 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-31mem-cache: mark block as dirty when handling SW prefetchTiago Mück
This addresses the issue described in 64687ee mem-cache: Mark block as dirty after a SWPrefetchEXResp. Previous patch misses cases when the prefetch response is ReadExResp or UpgradeResp. Also, marking the block as dirty in serviceMSHRTargets instead of in handleFill covers cases when the prefetch is coalesced with other requests. Change-Id: I2b377fdd240eb0f09e720b6bb284dee6545925ce Signed-off-by: Tiago Mück <tiago.muck@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19688 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-31mem-cache: Fix set and way of sub-entriesDaniel R. Carvalho
Set and way of sub-entries were not being set previously. They must be set after the sub-blocks have been assigned to the main block. Change-Id: I7b6921b8437b29c472d691cd78cf20f2bb6c7e07 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19669 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-17mem-cache: Create CPack compressorDaniel R. Carvalho
Implementation of C-Pack, as described in "C-Pack: A High- Performance Microprocessor Cache Compression Algorithm". C-Pack uses pattern matching schemes to detect and compress frequently appearing data patterns. As in the original paper, it divides the input in 32-bit words, and uses 6 patterns to match with its dictionary. For the patterns, each letter represents a byte: Z is a null byte, M is a dictionary match, X is a new value. The patterns are ZZZZ, XXXX, MMMM, MMXX, ZZZX, MMMX. Change-Id: I2efc9db2c862620dcc1155300e39be558f9017e0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11105 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-04Revert "mem-cache: Remove writebacks packet list"Daniel Carvalho
This reverts commit bf0a722acdd8247602e83720a5f81a0b69c76250. Reason for revert: This patch introduces a bug: The problem here is that the insertion of block A may cause the eviction of block B, which on the lower level may cause the eviction of block A. Since A is not marked as present yet, A is "safely" removed from the snoop filter However, by reverting it, using atomic and a Tags sub-class that can generate multiple evictions at once becomes broken when using Atomic mode and shall be fixed in a future patch. Change-Id: I5b27e54b54ae5b50255588835c1a2ebf3015f002 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19088 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29mem-cache: Accuracy-based rate control for prefetchersJavier Bueno
Added a mechanism to control the number of prefetches generated based in the effectiveness of the prefetches generated so far. Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18808 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-29mem-cache: Support for page crossing prefetchesJavier Bueno
Prefetchers can now issue hardware prefetch requests that go beyond the boundaries of the system page. Page crossing references will need to look up the TLBs to be able to compute the physical address to be prefetched. Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14620 Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
2019-05-20mem-cache: Add multi-prefetcher adaptorAndreas Sandberg
This patch adds a meta-prefetcher that enables gem5's cache models to connect to multiple prefetchers. Sub-prefetchers still use the probes-based interface and training can be controlled independently. However, when the cache requests a prefetch packet, the adaptor traverses the priority list of prefetchers and uses the first prefetcher that is able to generate a prefetch. Kudos to Mitch Hayenga for the original version of this patch. Change-Id: I25569a834997e5404c7183ec995d212912c5dcdf Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18868 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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