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Age
Commit message (
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Author
2015-03-27
mem: Support any number of master-IDs in stride prefetcher
Stephan Diestelhorst
2015-03-27
mem: Allocate cache writebacks before new MSHRs
Andreas Hansson
2015-03-27
mem: Cleanup flow for uncacheable accesses
Andreas Hansson
2015-03-27
mem: Ignore uncacheable MSHRs when finding matches
Andreas Hansson
2015-03-27
mem: Remove redundant allocateUncachedReadBuffer in cache
Andreas Hansson
2015-03-27
mem: Modernise MSHR iterators to C++11
Andreas Hansson
2015-03-27
mem: Align all MSHR entries to block boundaries
Andreas Hansson
2015-03-27
mem: Rename PREFETCH_SNOOP_SQUASH flag to BLOCK_CACHED
Ali Jafri
2015-03-19
mem: Use emplace front/back for deferred packets
Andreas Hansson
2015-02-11
mem: remove redundant test in in Cache::recvTimingResp()
Steve Reinhardt
2015-02-11
mem: add local var in Cache::recvTimingResp()
Steve Reinhardt
2015-03-14
mem: clean up write buffer check in Cache::handleSnoop()
Steve Reinhardt
2015-03-02
mem: Unify all cache DPRINTF address formatting
Andreas Hansson
2015-03-02
mem: Fix cache MSHR conflict determination
Andreas Hansson
2015-03-02
mem: Add option to force in-order insertion in PacketQueue
Stephan Diestelhorst
2015-03-02
mem: Downstream components consumes new crossbar delays
Marco Balboni
2015-03-02
mem: Tidy up the cache debug messages
Andreas Hansson
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2015-03-02
mem: Fix prefetchSquash + memInhibitAsserted bug
Ali Jafri
2015-02-11
mem: Clarification of packet crossbar timings
Marco Balboni
2015-02-11
mem: Clarify usage of latency in the cache
Marco Balboni
2015-02-03
mem: Clarify express snoop behaviour
Andreas Hansson
2015-02-03
mem: Clarify cache behaviour for pending dirty responses
Andreas Hansson
2015-01-22
mem: Remove Packet source from ForwardResponseRecord
Andreas Hansson
2015-01-20
mem: Fix bug in cache request retry mechanism
Andreas Hansson
2014-12-23
mem: Change prefetcher to use random_mt
Mitch Hayenga
2014-12-23
mem: Hide WriteInvalidate requests from prefetchers
Curtis Dunham
2014-12-23
mem: Fix event scheduling issue for prefetches
Mitch Hayenga
2014-12-23
mem: Fix bug relating to writebacks and prefetches
Mitch Hayenga
2014-12-23
mem: Rework the structuring of the prefetchers
Mitch Hayenga
2014-12-23
mem: Add parameter to reserve MSHR entries for demand access
Mitch Hayenga
2014-12-02
mem: Support WriteInvalidate (again)
Curtis Dunham
2014-12-02
mem: Remove WriteInvalidate support
Curtis Dunham
2014-12-02
mem: Clean up packet data allocation
Andreas Hansson
2014-12-02
mem: Cleanup Packet::checkFunctional and hasData usage
Andreas Hansson
2014-12-02
mem: Make the requests carried by packets const
Andreas Hansson
2014-12-02
mem: Add checks and explanation for assertMemInhibit usage
Andreas Hansson
2014-12-02
mem: Remove redundant Packet::allocate calls
Andreas Hansson
2014-12-02
mem: Add const getters for write packet data
Andreas Hansson
2014-10-29
arm, mem: Fix drain bug and provide drain prints for more components.
Ali Saidi
2014-10-21
mem: don't inhibit WriteInv's or defer snoops on their MSHRs
Curtis Dunham
2014-10-29
mem: have WriteInvalidate obsolete MSHRs
Curtis Dunham
2014-10-16
mem: Dynamically determine page bytes in memory components
Andreas Hansson
2014-10-09
mem: Add packet sanity checks to cache and MSHRs
Andreas Hansson
2014-09-27
misc: Fix a bunch of minor issues identified by static analysis
Andreas Hansson
2014-09-20
mem: Rename Bus to XBar to better reflect its behaviour
Andreas Hansson
2014-09-20
mem: Remove the GHB prefetcher from the source tree
Mitch Hayenga
2014-09-19
misc: Remove assertions ensuring unsigned values >= 0
Andreas Hansson
2014-09-19
mem: Add checks to sendTimingReq in cache
Andreas Hansson
2014-09-09
misc: Fix a number of unitialised variables and members
Andreas Hansson
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