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Modify second chance replacement policy so that entries are inserted
without a second chance. Previously, the second chance bit was set
to true when a cache line was inserted. So the cache line would gain
its second chance when inserting. This is wrong because the cache
block will only get a second chance when it hits.
Here's a quoted citation for the second chance replacement policy:
"Whenever the algorithm examines a page entry, it extracts the associated
usage bit and enters it into the high-order position of a k-bit shift
register after shifting the contents of the register one bit-position
lower. Then if the shift register is nonzero, the page is retained; if the
shift register is zero, the page is replaced by the new page. In either
case the usage bit for the page is turned off and the circular list
pointer is advanced."
(A Paging Experiment with the Multics System, FJ Corbato, 1968)
Change-Id: I0d07e56aa16c67dd36e0d490c3f457f91e46f320
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20882
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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The lastTouchTick is set to 0 when instantiate. This will cause the
candidate[0] to get evicted over and over again in MRU replacement
policy. To resolve this, break the search loop whenever it finds a
cold cache line.
Change-Id: I33aa57ebe0efca15986f62c3ae10a146bd2b779f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20881
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
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Add support in Ruby to use all replacement policies in Classic.
Furthermore, if new replacement policies are added to the
Classic system, the Ruby system will recognize new policies
without any other changes in Ruby system. The following list
all the major changes:
* Make Ruby cache entries (AbstractCacheEntry) inherit from
Classic cache entries (ReplaceableEntry). By doing this,
replacement policies can use cache entries from Ruby caches.
AccessPermission and print function are moved from
AbstractEntry to AbstractCacheEntry, so AbstractEntry is no
longer needed.
* DirectoryMemory and all SLICC files are changed to use
AbstractCacheEntry as their cache entry interface. So do the
python files in mem/slicc/ast which check the entry
interface.
* "main='false'" argument is added to the protocol files where
the DirectoryEntry is defined. This change helps
differentiate DirectoryEntry from CacheEntry because they are
both the instances of AbstractCacheEntry now.
* Use BaseReplacementPolicy in Ruby caches instead of
AbstractReplacementPolicy so that Ruby caches will recognize
the replacement policies from Classic.
* Add getLastAccess() and useOccupancy() function to Classic
system so that Ruby caches can use them. Move lastTouchTick
to ReplacementData struct because it's needed by
getLastAccess() to return the correct value.
* Add a 2-dimensional array of ReplacementData in Ruby caches
to store information for different replacement policies. Note
that, unlike Classic caches, where policy information is
stored in cache entries, the policy information needs to be
stored in a new 2-dimensional array. This is due to Ruby
caches deleting the cache entry every time the corresponding
cache line get evicted.
Change-Id: Idff6fdd2102a552c103e9d5f31f779aae052943f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20879
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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When a writeback needs to be allocated the whenReady field of the
block is not set, and therefore its access latency calculation
uses the previously invalidated value (MaxTick), significantly
delaying execution.
This is fixed by assuming that the data write portion of a write
access is done regardless of previous writes, and that only the
tag latency is important for the critical path latency calculation.
Change-Id: I739132a2deab6eb4c46d084f4ee6dd65177873fd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20068
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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This change puts cache and tag stats into a Stats::Group struct. This
makes it easier to identify stat updates (they are prefixed with
stat.) and adds hierarchy information for output formats that need it.
Change-Id: I2b8e9138f1cb977abb445ec864d80a79b588481d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21140
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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The bitmask field indicates to which base a delta refers, and in
the original paper it is fixed and proportional to the highest
number of bases allowed in the compressed data.
Change-Id: I271bf2e19e0765de52b933eaf6d4fcc2ce25d185
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19748
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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Use SatCounter in RRIP's RRPV. As such, move validation functionality
to a proper variable.
Change-Id: I142db2b7f6cd518ac3a2b68c9ed48005402b3464
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20452
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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The Port class has assumed all the duties of the less generic
Base*Port classes, making them unnecessary. Since they don't add
anything but make the code more complex, this change eliminates them.
Change-Id: Ibb9c56def04465f353362595c1f1c5ac5083e5e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20236
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
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ReplaceableEntry contains a virtual method, yet its destructor
was not virtual, causing errors in some compilers.
Change-Id: I13deec843f4007d9deb924882a8d98ff6a89c84f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19808
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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This addresses the issue described in
64687ee mem-cache: Mark block as dirty after a SWPrefetchEXResp.
Previous patch misses cases when the prefetch response is ReadExResp or
UpgradeResp. Also, marking the block as dirty in serviceMSHRTargets
instead of in handleFill covers cases when the prefetch is coalesced with
other requests.
Change-Id: I2b377fdd240eb0f09e720b6bb284dee6545925ce
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19688
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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Set and way of sub-entries were not being set previously.
They must be set after the sub-blocks have been assigned
to the main block.
Change-Id: I7b6921b8437b29c472d691cd78cf20f2bb6c7e07
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19669
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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Implementation of C-Pack, as described in "C-Pack: A High-
Performance Microprocessor Cache Compression Algorithm".
C-Pack uses pattern matching schemes to detect and compress
frequently appearing data patterns. As in the original paper,
it divides the input in 32-bit words, and uses 6 patterns to
match with its dictionary.
For the patterns, each letter represents a byte: Z is a null
byte, M is a dictionary match, X is a new value. The patterns
are ZZZZ, XXXX, MMMM, MMXX, ZZZX, MMMX.
Change-Id: I2efc9db2c862620dcc1155300e39be558f9017e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11105
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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This reverts commit bf0a722acdd8247602e83720a5f81a0b69c76250.
Reason for revert: This patch introduces a bug:
The problem here is that the insertion of block A may cause the
eviction of block B, which on the lower level may cause the
eviction of block A. Since A is not marked as present yet, A is
"safely" removed from the snoop filter
However, by reverting it, using atomic and a Tags sub-class that
can generate multiple evictions at once becomes broken when using
Atomic mode and shall be fixed in a future patch.
Change-Id: I5b27e54b54ae5b50255588835c1a2ebf3015f002
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19088
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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Added a mechanism to control the number of prefetches generated
based in the effectiveness of the prefetches generated so far.
Change-Id: I33af82546f74a5b5ab372c28574b76dd9a1bd46a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18808
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Prefetchers can now issue hardware prefetch requests that go beyond
the boundaries of the system page. Page crossing references will need
to look up the TLBs to be able to compute the physical address to be
prefetched.
Change-Id: Ib56374097e3b7dc87414139d210ea9272f96b06b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14620
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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This patch adds a meta-prefetcher that enables gem5's cache models to
connect to multiple prefetchers. Sub-prefetchers still use the
probes-based interface and training can be controlled
independently. However, when the cache requests a prefetch packet, the
adaptor traverses the priority list of prefetchers and uses the first
prefetcher that is able to generate a prefetch.
Kudos to Mitch Hayenga for the original version of this patch.
Change-Id: I25569a834997e5404c7183ec995d212912c5dcdf
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18868
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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This code will be preserved through version control, but otherwise
creates clutter and will rot in place since it's never compiled.
Change-Id: Id265f6deac445116843956ea5cf1210d8127274e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18608
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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Many prefetchers re-implement saturating counters with ints. Make
them use SatCounters instead.
Added missing operators and constructors to SatCounter for that to
be possible and their respective tests.
Change-Id: I36f10c89c27c9b3d1bf461e9ea546920f6ebb888
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17995
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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This changeset adds support for partial (or masked) loads/stores, i.e.
loads/stores that can disable accesses to individual bytes within the
target address range. In addition, this changeset extends the code to
crack memory accesses across most CPU models (TimingSimpleCPU still
TBD), so that arbitrarily wide memory accesses are supported. These
changes are required for supporting ISAs with wide vectors.
Additional authors:
- Gabor Dozsa <gabor.dozsa@arm.com>
- Tiago Muck <tiago.muck@arm.com>
Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13518
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Previously all atomic writebacks concerned a single block,
therefore, when a block was evicted, no other block would be
pending eviction. With sector tags (and compression),
however, a single replacement can generate many evictions.
This can cause problems, since a writeback that evicts a block
may evict blocks in the lower cache. If one of these conflict
with one of the blocks pending eviction in the higher level, the
snoop must inform it to the lower level. Since atomic mode does
not have a writebuffer, this kind of conflict wouldn't be noticed.
Therefore, instead of evicting multiple blocks at once, we
do it one by one.
Change-Id: I2fc2f9eb0f26248ddf91adbe987d158f5a2e592b
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18209
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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When a block in compressed form is overwriten, it may change
its size. If the new compressed size is bigger, and the total
size becomes bigger than the block size, one or more blocks
will have to be evicted. This is called data expansion, or
fat writes.
This change assumes that a first level cache cannot have a
compressor, since otherwise data expansion should have been
handled for atomic operations and writes. As such, data
expansions should only be seen on writebacks. As writebacks
are forwarded to the next level when failed, there should
be no data expansions when servicing misses either.
This patch adds the functionality to handle data expansions
by evicting the co-allocated blocks to make room for an
expanded block.
Change-Id: I0bd77bf6446bfae336889940b2f75d6f0c87e533
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12087
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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Implement a co-allocation function in compressed tags, so
that compressed blocks can be co-allocated in a superblock.
Co-allocation is possible when compression ratio (CR) blocks
that share a superblock tag can be compressed to up to (100/CR)%
of their size.
Change-Id: I937cc1fcbb488e70309cb5478c12db65f1b4b23f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11411
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Add a compressor to the base cache class and compress within
block allocation and decompress on writebacks.
This change does not implement data expansion (fat writes) yet,
nor it adds the compression latency to the block write time.
Change-Id: Ie36db65f7487c9b05ec4aedebc2c7651b4cb4821
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11410
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Implement Base-Delta-Immediate compression, as described in
'Base-Delta-Immediate Compression: Practical Data Compression
for On-Chip Caches'
Change-Id: I7980c340ab53a086b748f4b2108de4adc775fac8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11412
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Add compression statistics to the compressors. It tracks
the number of blocks that can fit into a certain power
of two size, and the number of decompressions.
For example, if a block is compressed to 100 bits, it will
belong to the 128-bits compression size. Although it could
also fit bigger sizes, they are not taken into account for
the stats (i.e., the 100-bit compression will fit only the
128-bits size, not 256 or higher).
We save stats for compressions that fail (i.e., compressed
size is bigger than original cache line size).
Change-Id: Idab71a40a660e33259908ccd880e42a880b5ee06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11103
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Create basic template for cache compressors. A basic compressor
must implement a compression and a decompression method.
Change-Id: I83dc4d2b8d2bc5ed9f760c938edfa4ebdd6b8583
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11100
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Add block size to findVictim. For standard caches it
will not be used. Compressed caches, however, need to
know the size of the compressed block to decide whether
a block is co-allocatable or not.
Change-Id: Id07f79763687b29f75d707c080fa9bd978a408aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11198
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Mohammad Seyedzadeh <sm.seyedzade@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Add a compression bit, decompression latency and compressed
block size and their respective getters and setters.
Change-Id: Ia9d8656552d60e8d4e85fe5379dd75fc5adb0abe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11102
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Create a debug flag for cache compression.
Change-Id: Id4b8e86d658d3aa550906ee0f8da3b54f4cdab7d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11104
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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Create a stub of a compression framework where we can have
multiple data blocks per tag entry. Only consecutive blocks
can share a tag as of now.
For each tag entry there can be multiple data blocks. We have
the same number of tags a conventional cache would have, but
we instantiate the maximum number of data blocks (according to
the compression ratio) per tag, to virtually implement
compression without increasing the complexity of the simulator.
Change-Id: I549940c7afb2f744ab293ff8bb283967e7551a11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10763
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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This is a workaround for a bug introduced from the change:
59e3585a8 arch-arm: We add PRFM PST instruction for arm
which can cause deadlocks in the memory system.
The design of the classic memory system in gem5 makes the folloing two
assumptions:
* A cache that fetches a block with an intention to modify it, becomes
the point of ordering and therefore commits to respond to any snoop
requests [1].
* A cache that fetches an exclusive copy of the block, does so with
the intention to modify it [2]. Immediately after it receives the
block, it will write to it and mark it as dirty. As the point of
ordering, it responds to any outstanding snoops.
The current implementation of prefetch exclusive request breaks the
second assumption. A cache can fetch an exclusive block without an
immediate intention to modify it. If the block is not modified, it
will not be marked as dirty. However, the cache has committed to
respond to outstanding snoops, and if the block is clean it
won't. This can result in deadlocks where a snoop gets stuck waiting
for responses.
One solution (implemented by this patch) is to unconditionally mark
the block dirty when filling due to a prefetch exclusive request.
This makes the PrefetchExReq behave like a WriteReq. However, as it
may mark as dirty a clean block, it creates the requirement for an
uncessary WritebackDirty in the future. In practice, this shouldn't be
a big problem unless the application is unnecessarily using prefetch
exclusive instructions.
Other solutions, would require deeper changes to the design of the
memory system to handle this properly.
[1]: When a cache commits to respond, it "informs" the xbar/PoC (point
of coherence) and the other caches of its intention to respond. As a
result the request will not be send to the main memory.
[2]: In fact the assumption is that in the needsWritable MSHR there is
at least one WriteReq before any snoops from other caches.
Change-Id: I378d3c0dadf25fc52e430b67102347b44d2f18ea
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17729
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
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MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
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Change-Id: I731d3ef021596450ac307461f215760a148bb28a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18348
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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Commit 7976b561de61b7523ca9a860154ad7ba701d12a7 tried fixing
replacement update when a single location can be associated to
multiple blocks.
Although the comment of the correct action was added, the proper
validation check was forgotten. This change adds that check and
moves doing the eviction to when there is a valid block.
Change-Id: I31d8bb914ccfd1849e9d97464d70a58a62f59533
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18210
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
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Replacements should be increased when there is any evicted
block, which does not necessarily have to be the victim.
For example, assume a superblock contains 4 blocks, and both
A and C are stored compressed (belonging to SB_1). Then F,
from SB2 needs to make room by replacing SB1. If F map to
location 2, the number of replacements should be increased,
even though 2 had no valid blocks:
Tag Data Tag Data
|SB_1|--|A|X|C|X| --> |SB_2| |X|F|X|X|
1 2 3 4 1 2 3 4
Change-Id: I7b3735d28a35faa8d8fa613a1555bb258da65859
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18208
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
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The blk_addr is pkt->getBlockAddr(), and therefore can be
acquired internally, when needed, as long as the pkt is
provided.
Change-Id: I2780445d2a0cb9e27257961efc4f438cc19550e5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17537
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Having the caller decide the matching logic is error-prone, and
frequently ends up with the secure bit being forgotten. This
change adds matching functions to the QueueEntry to avoid this
problem.
As a side effect the signature of findPending has been changed.
Change-Id: I6e494a821c1e6e841ab103ec69632c0e1b269a08
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17530
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Add both block and non-block-aligned packet matching functions,
so that both address and secure bits are checked when checking
whether a packet matches a request.
Change-Id: Id0069befb925d112e06f250741cb47d9dfa249cc
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17533
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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WriteQueueEntry's target has 100% functionality overlap with MSHR's,
therefore make it base to MSHR::Target.
Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Queue has several assumptions regarding its template parameter,
so make sure they are fulfilled by forcing Entry to be derived
from QueueEntry.
Change-Id: I0203a62aec00c04ac89e9674d86a44a07f9f13ab
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17529
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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The RRPV values for RRIP and NRU replacment policies.
Long re-rereference interval was used instead of
distant re-rereference interval and vice-versa.
The btp value permit to choose beetwen distant and
long insertion ratio. A btp value of 0 force the
policy to always insert at a distant re-reference
interval and a btp value of 100 force the policy to
always insert at a long (intermediate) re-rereference
interval.
Change-Id: I516098f73942b769dcc31fe0edfe07c3e9c3effd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17851
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Previously satisfied clean requests would not snoop in-service
MSHRs. This is a problem when a clean request is also invalidating, in
which case we have to post-invalidate or post-downgrade outstanding
requests. This changes fixes this bug.
Change-Id: I31e42aa94dd3637b2818e00fbaae68c810145eaf
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17728
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
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std::abs doesn't accept unsigned long long, generating the error:
error: call to 'abs' is ambiguous
Use instead a compare-and-subtract idiom.
Also, Changed return type of distanceFromTrigger from unsigned int to Addr to
prevent overflow problems.
Change-Id: Ia7752c1c7a838f98e8c7ed6ade9f586f31bbcf7d
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17788
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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The preriodic event triggers an assertion due to an incorrect tick value to
schedule when restoring from a checkpoint.
Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17732
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Referencing BaseCPU is causing a compilation error when using the NULL ISA.
This patch changes the reference to a SimObject, which fixes the problem.
Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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An assertion ignored the case when an entry of the SP table had been invalidated.
Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Memory requests with a size non-power-of-two and less than 8 values were causing
a panic, but there these should be allowed and ignored by the prefetcher.
Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17733
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December).
Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM
International Symposium on Microarchitecture (pp. 152-162). ACM.
Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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The cache header was being included in the AMAP, although not
used, which resulted in slightly longer compilation time.
Change-Id: I3654bc719c6b5f558af116addae159301602a3cf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17711
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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Reference:
Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, and
Babak Falsafi. 2009. Spatio-temporal memory streaming.
In Proceedings of the 36th annual international symposium on
Computer architecture (ISCA '09). ACM, New York, NY, USA, 69-80.
Change-Id: I58cea1a7faa9391f8aa4469eb4973feabd31097a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16423
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
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