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path: root/src/mem/coherent_bus.cc
AgeCommit message (Expand)Author
2013-04-22mem: Adding verbose debug output in the memory systemUri Wiener
2013-03-26mem: Separate waiting for the bus and waiting for a peerAndreas Hansson
2013-02-19mem: Enforce strict use of busFirst- and busLastWordTimeAndreas Hansson
2013-02-19mem: Make packet bus-related time accounting relativeAndreas Hansson
2013-02-19sim: Make clock private and access using clockPeriod()Andreas Hansson
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-10-11Mem: Determine bus block size during initialisationAndreas Hansson
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Bus: Split the bus into separate request/response layersAndreas Hansson
2012-07-09Bus: Add a notion of layers to the busesAndreas Hansson
2012-07-09Bus: Replace tickNextIdle and inRetry with a state variableAndreas Hansson
2012-07-09Port: Add isSnooping to slave port (asking master port)Andreas Hansson
2012-05-31Bus: Split the bus into a non-coherent and coherent busAndreas Hansson