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path: root/src/mem/dram_ctrl.cc
AgeCommit message (Expand)Author
2019-10-29mem: Fix DRAM controller to operate on its own address spaceNikos Nikoleris
2019-10-03mem: Remove unused variableTommaso Marinelli
2019-09-30mem: Convert DRAM controller to new-style statsAndreas Sandberg
2019-06-06mem: Option to toggle DRAM low-power statesMatthew Poremba
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-19mem: Make DRAMCtrl::decodeAddr constDaniel R. Carvalho
2019-04-05mem: Reverse order of write/read mem queue checkJason Lowe-Power
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-01-17mem: Determine if a packet queue forces ordering at constructionNikos Nikoleris
2018-09-07mem: Make DRAMCtrl a QoS-aware Memory ControllerMatteo Andreozzi
2018-07-23mem: Rename Packet::checkFunctional to trySatisfyFunctionalRobert Kovacsics
2018-05-18mem: Add support for more flexible DRAM timing and topologiesWendy Elsasser
2018-05-18mem: Optimize self-refresh entryWendy Elsasser
2018-04-06mem: Remove unused 'using namespace'Daniel R. Carvalho
2017-11-16ext, mem: Pull DRAMPower SHA 90d6290 and rebaseRadhika Jagtap
2017-06-20mem: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2017-06-20mem: Move the Rank construction logic to the Rank constructorSean Wilson
2017-02-15mem: fix assertion in respondEventWendy Elsasser
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-10-13mem: Add DRAM low-power functionalityWendy Elsasser
2016-10-13mem: Add callback to compute stats prior to dump eventWendy Elsasser
2016-10-13mem: Modify drain to ensure banks and power are idledWendy Elsasser
2016-10-13mem: Sort memory commands and update DRAMPowerWendy Elsasser
2016-10-13mem: add DRAM powerdown timingOmar Naji
2016-02-10mem: Move the point of coherency to the coherent crossbarAndreas Hansson
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-11-06mem: Enforce insertion order on the cache response pathAli Jafri
2015-11-06mem: Align rules for sinking inhibited packets at the slaveAndreas Hansson
2015-11-06mem: Unify delayed packet deletionAndreas Hansson
2015-11-06misc: Appease clang static analyzerAndreas Hansson
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-03mem: Update DRAM command scheduler for bank groupsWendy Elsasser
2015-07-03mem: Avoid DRAM write queue iteration for merging and read lookupAndreas Hansson
2015-07-03mem: Add clean evicts to improve snoop filter trackingAli Jafri
2015-04-29mem: Simplify page close checks for adaptive policiesRizwana Begum
2015-03-02mem: Downstream components consumes new crossbar delaysMarco Balboni
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2015-01-20mem: Move DRAM interleaving check to initAndreas Hansson
2014-12-23config: Expose the DRAM ranks as a command-line optionAndreas Hansson
2014-12-23mem: Ensure DRAM controller is idle when in atomic modeAndreas Hansson
2014-12-23mem: Add rank-wise refresh to the DRAM controllerOmar Naji
2014-12-23mem: Fix a bug in the DRAM controller arbitrationOmar Naji
2014-12-02mem: Add a GDDR5 DRAM configOmar Naji
2014-10-29arm, mem: Fix drain bug and provide drain prints for more components.Ali Saidi
2014-10-20mem: Fix DRAM activationlLimit bugOmar Naji
2014-10-20mem: Add DRAM device size and check against configOmar Naji