| Age | Commit message (Expand) | Author |
|---|
| 2014-08-26 | mem: Fix address interleaving bug in DRAM controller | Andreas Hansson |
| 2014-06-30 | mem: DRAMPower trace output | Andreas Hansson |
| 2014-06-30 | mem: Add bank and rank indices as fields to the DRAM bank | Andreas Hansson |
| 2014-06-30 | mem: Extend DRAM row bits from 16 to 32 for larger densities | Andreas Hansson |
| 2014-05-09 | mem: Add DRAM cycle time | Andreas Hansson |
| 2014-05-09 | mem: Simplify DRAM response scheduling | Andreas Hansson |
| 2014-05-09 | mem: Add precharge all (PREA) to the DRAM controller | Andreas Hansson |
| 2014-05-09 | mem: Remove printing of DRAM params | Andreas Hansson |
| 2014-05-09 | mem: Add tRTP to the DRAM controller | Andreas Hansson |
| 2014-05-09 | mem: Merge DRAM latency calculation and bank state update | Andreas Hansson |
| 2014-05-09 | mem: Add tWR to DRAM activate and precharge constraints | Andreas Hansson |
| 2014-05-09 | mem: Merge DRAM page-management calculations | Andreas Hansson |
| 2014-05-09 | mem: Add DRAM power states to the controller | Andreas Hansson |
| 2014-05-09 | mem: Ensure DRAM refresh respects timings | Andreas Hansson |
| 2014-05-09 | mem: Make DRAM read/write switching less conservative | Andreas Hansson |
| 2014-03-23 | mem: Track DRAM read/write switching and add hysteresis | Andreas Hansson |
| 2014-03-23 | mem: Rename SimpleDRAM to a more suitable DRAMCtrl | Andreas Hansson |
