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path: root/src/mem/dram_ctrl.cc
AgeCommit message (Expand)Author
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20mem: Add DDR4 bank group timingWendy Elsasser
2014-09-20mem: Add memory rank-to-rank delayWendy Elsasser
2014-08-26mem: Fix address interleaving bug in DRAM controllerAndreas Hansson
2014-06-30mem: DRAMPower trace outputAndreas Hansson
2014-06-30mem: Add bank and rank indices as fields to the DRAM bankAndreas Hansson
2014-06-30mem: Extend DRAM row bits from 16 to 32 for larger densitiesAndreas Hansson
2014-05-09mem: Add DRAM cycle timeAndreas Hansson
2014-05-09mem: Simplify DRAM response schedulingAndreas Hansson
2014-05-09mem: Add precharge all (PREA) to the DRAM controllerAndreas Hansson
2014-05-09mem: Remove printing of DRAM paramsAndreas Hansson
2014-05-09mem: Add tRTP to the DRAM controllerAndreas Hansson
2014-05-09mem: Merge DRAM latency calculation and bank state updateAndreas Hansson
2014-05-09mem: Add tWR to DRAM activate and precharge constraintsAndreas Hansson
2014-05-09mem: Merge DRAM page-management calculationsAndreas Hansson
2014-05-09mem: Add DRAM power states to the controllerAndreas Hansson
2014-05-09mem: Ensure DRAM refresh respects timingsAndreas Hansson
2014-05-09mem: Make DRAM read/write switching less conservativeAndreas Hansson
2014-03-23mem: Track DRAM read/write switching and add hysteresisAndreas Hansson
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson