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path: root/src/mem/dram_ctrl.cc
AgeCommit message (Expand)Author
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-11-06mem: Enforce insertion order on the cache response pathAli Jafri
2015-11-06mem: Align rules for sinking inhibited packets at the slaveAndreas Hansson
2015-11-06mem: Unify delayed packet deletionAndreas Hansson
2015-11-06misc: Appease clang static analyzerAndreas Hansson
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Decouple draining from the SimObject hierarchyAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-03mem: Update DRAM command scheduler for bank groupsWendy Elsasser
2015-07-03mem: Avoid DRAM write queue iteration for merging and read lookupAndreas Hansson
2015-07-03mem: Add clean evicts to improve snoop filter trackingAli Jafri
2015-04-29mem: Simplify page close checks for adaptive policiesRizwana Begum
2015-03-02mem: Downstream components consumes new crossbar delaysMarco Balboni
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-11mem: Clarification of packet crossbar timingsMarco Balboni
2015-01-20mem: Move DRAM interleaving check to initAndreas Hansson
2014-12-23config: Expose the DRAM ranks as a command-line optionAndreas Hansson
2014-12-23mem: Ensure DRAM controller is idle when in atomic modeAndreas Hansson
2014-12-23mem: Add rank-wise refresh to the DRAM controllerOmar Naji
2014-12-23mem: Fix a bug in the DRAM controller arbitrationOmar Naji
2014-12-02mem: Add a GDDR5 DRAM configOmar Naji
2014-10-29arm, mem: Fix drain bug and provide drain prints for more components.Ali Saidi
2014-10-20mem: Fix DRAM activationlLimit bugOmar Naji
2014-10-20mem: Add DRAM device size and check against configOmar Naji
2014-10-16mem: Dynamically determine page bytes in memory componentsAndreas Hansson
2014-07-29mem: DRAMPower integration for on-line DRAM power statsOmar Naji
2014-09-20mem: Rename Bus to XBar to better reflect its behaviourAndreas Hansson
2014-09-20mem: Add DDR4 bank group timingWendy Elsasser
2014-09-20mem: Add memory rank-to-rank delayWendy Elsasser
2014-08-26mem: Fix address interleaving bug in DRAM controllerAndreas Hansson
2014-06-30mem: DRAMPower trace outputAndreas Hansson
2014-06-30mem: Add bank and rank indices as fields to the DRAM bankAndreas Hansson
2014-06-30mem: Extend DRAM row bits from 16 to 32 for larger densitiesAndreas Hansson
2014-05-09mem: Add DRAM cycle timeAndreas Hansson
2014-05-09mem: Simplify DRAM response schedulingAndreas Hansson
2014-05-09mem: Add precharge all (PREA) to the DRAM controllerAndreas Hansson
2014-05-09mem: Remove printing of DRAM paramsAndreas Hansson
2014-05-09mem: Add tRTP to the DRAM controllerAndreas Hansson
2014-05-09mem: Merge DRAM latency calculation and bank state updateAndreas Hansson
2014-05-09mem: Add tWR to DRAM activate and precharge constraintsAndreas Hansson
2014-05-09mem: Merge DRAM page-management calculationsAndreas Hansson
2014-05-09mem: Add DRAM power states to the controllerAndreas Hansson
2014-05-09mem: Ensure DRAM refresh respects timingsAndreas Hansson
2014-05-09mem: Make DRAM read/write switching less conservativeAndreas Hansson
2014-03-23mem: Track DRAM read/write switching and add hysteresisAndreas Hansson
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson