| Age | Commit message (Expand) | Author |
|---|
| 2017-06-20 | mem: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
| 2017-06-20 | mem: Move the Rank construction logic to the Rank constructor | Sean Wilson |
| 2017-02-15 | mem: fix assertion in respondEvent | Wendy Elsasser |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2016-10-13 | mem: Add DRAM low-power functionality | Wendy Elsasser |
| 2016-10-13 | mem: Add callback to compute stats prior to dump event | Wendy Elsasser |
| 2016-10-13 | mem: Modify drain to ensure banks and power are idled | Wendy Elsasser |
| 2016-10-13 | mem: Sort memory commands and update DRAMPower | Wendy Elsasser |
| 2016-10-13 | mem: add DRAM powerdown timing | Omar Naji |
| 2016-02-10 | mem: Move the point of coherency to the coherent crossbar | Andreas Hansson |
| 2016-02-06 | style: fix missing spaces in control statements | Steve Reinhardt |
| 2015-12-31 | mem: Make cache terminology easier to understand | Andreas Hansson |
| 2015-11-06 | mem: Enforce insertion order on the cache response path | Ali Jafri |
| 2015-11-06 | mem: Align rules for sinking inhibited packets at the slave | Andreas Hansson |
| 2015-11-06 | mem: Unify delayed packet deletion | Andreas Hansson |
| 2015-11-06 | misc: Appease clang static analyzer | Andreas Hansson |
| 2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
| 2015-07-07 | sim: Decouple draining from the SimObject hierarchy | Andreas Sandberg |
| 2015-07-07 | sim: Make the drain state a global typed enum | Andreas Sandberg |
| 2015-07-03 | mem: Update DRAM command scheduler for bank groups | Wendy Elsasser |
| 2015-07-03 | mem: Avoid DRAM write queue iteration for merging and read lookup | Andreas Hansson |
| 2015-07-03 | mem: Add clean evicts to improve snoop filter tracking | Ali Jafri |
| 2015-04-29 | mem: Simplify page close checks for adaptive policies | Rizwana Begum |
| 2015-03-02 | mem: Downstream components consumes new crossbar delays | Marco Balboni |
| 2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
| 2015-02-11 | mem: Clarification of packet crossbar timings | Marco Balboni |
| 2015-01-20 | mem: Move DRAM interleaving check to init | Andreas Hansson |
| 2014-12-23 | config: Expose the DRAM ranks as a command-line option | Andreas Hansson |
| 2014-12-23 | mem: Ensure DRAM controller is idle when in atomic mode | Andreas Hansson |
| 2014-12-23 | mem: Add rank-wise refresh to the DRAM controller | Omar Naji |
| 2014-12-23 | mem: Fix a bug in the DRAM controller arbitration | Omar Naji |
| 2014-12-02 | mem: Add a GDDR5 DRAM config | Omar Naji |
| 2014-10-29 | arm, mem: Fix drain bug and provide drain prints for more components. | Ali Saidi |
| 2014-10-20 | mem: Fix DRAM activationlLimit bug | Omar Naji |
| 2014-10-20 | mem: Add DRAM device size and check against config | Omar Naji |
| 2014-10-16 | mem: Dynamically determine page bytes in memory components | Andreas Hansson |
| 2014-07-29 | mem: DRAMPower integration for on-line DRAM power stats | Omar Naji |
| 2014-09-20 | mem: Rename Bus to XBar to better reflect its behaviour | Andreas Hansson |
| 2014-09-20 | mem: Add DDR4 bank group timing | Wendy Elsasser |
| 2014-09-20 | mem: Add memory rank-to-rank delay | Wendy Elsasser |
| 2014-08-26 | mem: Fix address interleaving bug in DRAM controller | Andreas Hansson |
| 2014-06-30 | mem: DRAMPower trace output | Andreas Hansson |
| 2014-06-30 | mem: Add bank and rank indices as fields to the DRAM bank | Andreas Hansson |
| 2014-06-30 | mem: Extend DRAM row bits from 16 to 32 for larger densities | Andreas Hansson |
| 2014-05-09 | mem: Add DRAM cycle time | Andreas Hansson |
| 2014-05-09 | mem: Simplify DRAM response scheduling | Andreas Hansson |
| 2014-05-09 | mem: Add precharge all (PREA) to the DRAM controller | Andreas Hansson |
| 2014-05-09 | mem: Remove printing of DRAM params | Andreas Hansson |
| 2014-05-09 | mem: Add tRTP to the DRAM controller | Andreas Hansson |
| 2014-05-09 | mem: Merge DRAM latency calculation and bank state update | Andreas Hansson |
