gem5 - gem5

Age	Commit message (Expand)	Author
2019-10-29	mem: Fix DRAM controller to operate on its own address space	Nikos Nikoleris
2019-10-03	mem: Remove unused variable	Tommaso Marinelli
2019-09-30	mem: Convert DRAM controller to new-style stats	Andreas Sandberg
2019-06-06	mem: Option to toggle DRAM low-power states	Matthew Poremba
2019-04-28	mem: Minimize the use of MemObject.	Gabe Black
2019-04-19	mem: Make DRAMCtrl::decodeAddr const	Daniel R. Carvalho
2019-04-05	mem: Reverse order of write/read mem queue check	Jason Lowe-Power
2019-03-19	arch, cpu, dev, gpu, mem, sim, python: start using getPort.	Gabe Black
2019-01-17	mem: Determine if a packet queue forces ordering at construction	Nikos Nikoleris
2018-09-07	mem: Make DRAMCtrl a QoS-aware Memory Controller	Matteo Andreozzi
2018-07-23	mem: Rename Packet::checkFunctional to trySatisfyFunctional	Robert Kovacsics
2018-05-18	mem: Add support for more flexible DRAM timing and topologies	Wendy Elsasser
2018-05-18	mem: Optimize self-refresh entry	Wendy Elsasser
2018-04-06	mem: Remove unused 'using namespace'	Daniel R. Carvalho
2017-11-16	ext, mem: Pull DRAMPower SHA 90d6290 and rebase	Radhika Jagtap
2017-06-20	mem: Replace EventWrapper use with EventFunctionWrapper	Sean Wilson
2017-06-20	mem: Move the Rank construction logic to the Rank constructor	Sean Wilson
2017-02-15	mem: fix assertion in respondEvent	Wendy Elsasser
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2016-10-13	mem: Add DRAM low-power functionality	Wendy Elsasser
2016-10-13	mem: Add callback to compute stats prior to dump event	Wendy Elsasser
2016-10-13	mem: Modify drain to ensure banks and power are idled	Wendy Elsasser
2016-10-13	mem: Sort memory commands and update DRAMPower	Wendy Elsasser
2016-10-13	mem: add DRAM powerdown timing	Omar Naji
2016-02-10	mem: Move the point of coherency to the coherent crossbar	Andreas Hansson
2016-02-06	style: fix missing spaces in control statements	Steve Reinhardt
2015-12-31	mem: Make cache terminology easier to understand	Andreas Hansson
2015-11-06	mem: Enforce insertion order on the cache response path	Ali Jafri
2015-11-06	mem: Align rules for sinking inhibited packets at the slave	Andreas Hansson
2015-11-06	mem: Unify delayed packet deletion	Andreas Hansson
2015-11-06	misc: Appease clang static analyzer	Andreas Hansson
2015-07-07	sim: Refactor and simplify the drain API	Andreas Sandberg
2015-07-07	sim: Decouple draining from the SimObject hierarchy	Andreas Sandberg
2015-07-07	sim: Make the drain state a global typed enum	Andreas Sandberg
2015-07-03	mem: Update DRAM command scheduler for bank groups	Wendy Elsasser
2015-07-03	mem: Avoid DRAM write queue iteration for merging and read lookup	Andreas Hansson
2015-07-03	mem: Add clean evicts to improve snoop filter tracking	Ali Jafri
2015-04-29	mem: Simplify page close checks for adaptive policies	Rizwana Begum
2015-03-02	mem: Downstream components consumes new crossbar delays	Marco Balboni
2015-03-02	mem: Split port retry for all different packet classes	Andreas Hansson
2015-02-11	mem: Clarification of packet crossbar timings	Marco Balboni
2015-01-20	mem: Move DRAM interleaving check to init	Andreas Hansson
2014-12-23	config: Expose the DRAM ranks as a command-line option	Andreas Hansson
2014-12-23	mem: Ensure DRAM controller is idle when in atomic mode	Andreas Hansson
2014-12-23	mem: Add rank-wise refresh to the DRAM controller	Omar Naji
2014-12-23	mem: Fix a bug in the DRAM controller arbitration	Omar Naji
2014-12-02	mem: Add a GDDR5 DRAM config	Omar Naji
2014-10-29	arm, mem: Fix drain bug and provide drain prints for more components.	Ali Saidi
2014-10-20	mem: Fix DRAM activationlLimit bug	Omar Naji
2014-10-20	mem: Add DRAM device size and check against config	Omar Naji