| Age | Commit message (Expand) | Author |
|---|---|---|
| 2014-05-09 | mem: Add DRAM cycle time | Andreas Hansson |
| 2014-05-09 | mem: Simplify DRAM response scheduling | Andreas Hansson |
| 2014-05-09 | mem: Remove printing of DRAM params | Andreas Hansson |
| 2014-05-09 | mem: Add tRTP to the DRAM controller | Andreas Hansson |
| 2014-05-09 | mem: Merge DRAM latency calculation and bank state update | Andreas Hansson |
| 2014-05-09 | mem: Add tWR to DRAM activate and precharge constraints | Andreas Hansson |
| 2014-05-09 | mem: Add DRAM power states to the controller | Andreas Hansson |
| 2014-05-09 | mem: Ensure DRAM refresh respects timings | Andreas Hansson |
| 2014-05-09 | mem: Make DRAM read/write switching less conservative | Andreas Hansson |
| 2014-03-23 | mem: Track DRAM read/write switching and add hysteresis | Andreas Hansson |
| 2014-03-23 | mem: Rename SimpleDRAM to a more suitable DRAMCtrl | Andreas Hansson |
 |
index : gem5 | |
| gem5 |
| summaryrefslogtreecommitdiff |