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mem
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dram_ctrl.hh
Age
Commit message (
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Author
2015-10-12
misc: Remove redundant compiler-specific defines
Andreas Hansson
2015-07-07
sim: Refactor and simplify the drain API
Andreas Sandberg
2015-07-03
mem: Update DRAM command scheduler for bank groups
Wendy Elsasser
2015-07-03
mem: Avoid DRAM write queue iteration for merging and read lookup
Andreas Hansson
2015-03-02
mem: Split port retry for all different packet classes
Andreas Hansson
2014-12-23
mem: Ensure DRAM controller is idle when in atomic mode
Andreas Hansson
2014-12-23
mem: Add rank-wise refresh to the DRAM controller
Omar Naji
2014-10-20
mem: Add DRAM device size and check against config
Omar Naji
2014-07-29
mem: DRAMPower integration for on-line DRAM power stats
Omar Naji
2014-09-20
mem: Add DDR4 bank group timing
Wendy Elsasser
2014-09-20
mem: Add memory rank-to-rank delay
Wendy Elsasser
2014-08-26
mem: Update DRAM controller comments
Andreas Hansson
2014-08-26
mem: Fix address interleaving bug in DRAM controller
Andreas Hansson
2014-06-30
mem: DRAMPower trace output
Andreas Hansson
2014-06-30
mem: Add bank and rank indices as fields to the DRAM bank
Andreas Hansson
2014-06-30
mem: Extend DRAM row bits from 16 to 32 for larger densities
Andreas Hansson
2014-05-09
mem: Add DRAM cycle time
Andreas Hansson
2014-05-09
mem: Simplify DRAM response scheduling
Andreas Hansson
2014-05-09
mem: Remove printing of DRAM params
Andreas Hansson
2014-05-09
mem: Add tRTP to the DRAM controller
Andreas Hansson
2014-05-09
mem: Merge DRAM latency calculation and bank state update
Andreas Hansson
2014-05-09
mem: Add tWR to DRAM activate and precharge constraints
Andreas Hansson
2014-05-09
mem: Add DRAM power states to the controller
Andreas Hansson
2014-05-09
mem: Ensure DRAM refresh respects timings
Andreas Hansson
2014-05-09
mem: Make DRAM read/write switching less conservative
Andreas Hansson
2014-03-23
mem: Track DRAM read/write switching and add hysteresis
Andreas Hansson
2014-03-23
mem: Rename SimpleDRAM to a more suitable DRAMCtrl
Andreas Hansson