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path: root/src/mem/dram_ctrl.hh
AgeCommit message (Expand)Author
2019-10-29mem: Fix DRAM controller to operate on its own address spaceNikos Nikoleris
2019-09-30mem: Convert DRAM controller to new-style statsAndreas Sandberg
2019-06-06mem: Option to toggle DRAM low-power statesMatthew Poremba
2019-04-19mem: Make DRAMCtrl::decodeAddr constDaniel R. Carvalho
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2018-09-07mem: Make DRAMCtrl a QoS-aware Memory ControllerMatteo Andreozzi
2018-05-18mem: Add support for more flexible DRAM timing and topologiesWendy Elsasser
2018-05-18mem: Optimize self-refresh entryWendy Elsasser
2017-11-16ext, mem: Pull DRAMPower SHA 90d6290 and rebaseRadhika Jagtap
2017-06-20mem: Replace EventWrapper use with EventFunctionWrapperSean Wilson
2017-06-20mem: Move the Rank construction logic to the Rank constructorSean Wilson
2016-10-13mem: Add DRAM low-power functionalityWendy Elsasser
2016-10-13mem: Add callback to compute stats prior to dump eventWendy Elsasser
2016-10-13mem: Modify drain to ensure banks and power are idledWendy Elsasser
2016-10-13mem: Sort memory commands and update DRAMPowerWendy Elsasser
2016-10-13mem: add DRAM powerdown timingOmar Naji
2016-07-01ext: Update DRAMPowerMatthias Jung
2015-11-06mem: Unify delayed packet deletionAndreas Hansson
2015-10-12misc: Add explicit overrides and fix other clang >= 3.5 issuesAndreas Hansson
2015-10-12misc: Remove redundant compiler-specific definesAndreas Hansson
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-03mem: Update DRAM command scheduler for bank groupsWendy Elsasser
2015-07-03mem: Avoid DRAM write queue iteration for merging and read lookupAndreas Hansson
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2014-12-23mem: Ensure DRAM controller is idle when in atomic modeAndreas Hansson
2014-12-23mem: Add rank-wise refresh to the DRAM controllerOmar Naji
2014-10-20mem: Add DRAM device size and check against configOmar Naji
2014-07-29mem: DRAMPower integration for on-line DRAM power statsOmar Naji
2014-09-20mem: Add DDR4 bank group timingWendy Elsasser
2014-09-20mem: Add memory rank-to-rank delayWendy Elsasser
2014-08-26mem: Update DRAM controller commentsAndreas Hansson
2014-08-26mem: Fix address interleaving bug in DRAM controllerAndreas Hansson
2014-06-30mem: DRAMPower trace outputAndreas Hansson
2014-06-30mem: Add bank and rank indices as fields to the DRAM bankAndreas Hansson
2014-06-30mem: Extend DRAM row bits from 16 to 32 for larger densitiesAndreas Hansson
2014-05-09mem: Add DRAM cycle timeAndreas Hansson
2014-05-09mem: Simplify DRAM response schedulingAndreas Hansson
2014-05-09mem: Remove printing of DRAM paramsAndreas Hansson
2014-05-09mem: Add tRTP to the DRAM controllerAndreas Hansson
2014-05-09mem: Merge DRAM latency calculation and bank state updateAndreas Hansson
2014-05-09mem: Add tWR to DRAM activate and precharge constraintsAndreas Hansson
2014-05-09mem: Add DRAM power states to the controllerAndreas Hansson
2014-05-09mem: Ensure DRAM refresh respects timingsAndreas Hansson
2014-05-09mem: Make DRAM read/write switching less conservativeAndreas Hansson
2014-03-23mem: Track DRAM read/write switching and add hysteresisAndreas Hansson
2014-03-23mem: Rename SimpleDRAM to a more suitable DRAMCtrlAndreas Hansson