| Age | Commit message (Expand) | Author |
|---|
| 2019-04-28 | mem: Minimize the use of MemObject. | Gabe Black |
| 2019-03-19 | arch, cpu, dev, gpu, mem, sim, python: start using getPort. | Gabe Black |
| 2018-07-23 | mem: Rename Packet::checkFunctional to trySatisfyFunctional | Robert Kovacsics |
| 2017-06-20 | mem: Replace EventWrapper use with EventFunctionWrapper | Sean Wilson |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2015-12-31 | mem: Make cache terminology easier to understand | Andreas Hansson |
| 2015-11-06 | mem: Align rules for sinking inhibited packets at the slave | Andreas Hansson |
| 2015-11-06 | mem: Unify delayed packet deletion | Andreas Hansson |
| 2015-07-13 | mem: Updated DRAMSim2 wrapper to new drain API | Andreas Hansson |
| 2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
| 2015-07-07 | sim: Make the drain state a global typed enum | Andreas Sandberg |
| 2015-03-02 | mem: Downstream components consumes new crossbar delays | Marco Balboni |
| 2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
| 2015-02-11 | mem: Clarification of packet crossbar timings | Marco Balboni |
| 2014-10-16 | mem: Dynamically determine page bytes in memory components | Andreas Hansson |
| 2014-09-20 | mem: Rename Bus to XBar to better reflect its behaviour | Andreas Hansson |
| 2014-08-26 | mem: Fix DRAMSim2 cycle check when restoring from checkpoint | Andreas Hansson |
| 2014-02-18 | mem: Add a wrapped DRAMSim2 memory controller | Andreas Hansson |
