gem5 - gem5

Age	Commit message (Collapse)	Author
2014-11-23	mem: Page Table map api modification	Alexandru Dutu
	This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes.
2014-11-23	mem: Multi Level Page Table bug fix	Alexandru Dutu
	The multi level page table was giving false positives for already mapped translations. This patch fixes the bogus behavior.
2014-11-23	mem: Page Table long lines	Alexandru Dutu
	Trimmed down all the lines greater than 78 characters.
2014-09-03	arch: Cleanup unused ISA traits constants	Andreas Hansson
	This patch prunes unused values, and also unifies how the values are defined (not using an enum for ALPHA), aligning the use of int vs Addr etc. The patch also removes the duplication of PageBytes/PageShift and VMPageSize/LogVMPageSize. For all ISAs the two pairs had identical values and the latter has been removed.
2014-04-01	mem: adding a multi-level page table class	Alexandru
	This patch defines a multi-level page table class that stores the page table in system memory, consistent with ISA specifications. In this way, cpu models that use the actual hardware to execute (e.g. KvmCPU), are able to traverse the page table.