| Age | Commit message (Expand) | Author |
|---|---|---|
| 2013-07-18 | mem: Set the cache line size on a system level | Andreas Hansson |
| 2013-05-30 | mem: Make the buses multi layered | Andreas Hansson |
| 2013-05-30 | mem: Add basic stats to the buses | Uri Wiener |
| 2013-03-26 | mem: Separate waiting for the bus and waiting for a peer | Andreas Hansson |
| 2013-02-19 | sim: Make clock private and access using clockPeriod() | Andreas Hansson |
| 2012-11-02 | sim: Move the draining interface into a separate base class | Andreas Sandberg |
| 2012-10-11 | Mem: Determine bus block size during initialisation | Andreas Hansson |
| 2012-07-09 | Bus: Split the bus into separate request/response layers | Andreas Hansson |
| 2012-07-09 | Bus: Add a notion of layers to the buses | Andreas Hansson |
| 2012-07-09 | Port: Make getAddrRanges const | Andreas Hansson |
| 2012-06-29 | Bus: enable non/coherent buses sub-classes | Uri Wiener |
| 2012-05-31 | Bus: Split the bus into a non-coherent and coherent bus | Andreas Hansson |
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