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2007-06-21Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920
2007-06-21Getting closer...Steve Reinhardt
configs/example/memtest.py: Add progress interval option. src/base/traceflags.py: Add MemTest flag. src/cpu/memtest/memtest.cc: Clean up tracing. src/cpu/memtest/memtest.hh: Get rid of unused code. --HG-- extra : convert_revision : 92bd8241a6c90bfb6d908e5a5132cbdb500cbb87
2007-06-21Use FastAlloc for Packet, Request, CoherenceState, and SenderState so we ↵Ali Saidi
don't spend so much time calling malloc() --HG-- extra : convert_revision : a946564eee46ed7d2aed41c32d488ca7f036c32f
2007-06-17More major reorg of cache. Seems to work for atomic mode now,Steve Reinhardt
timing mode still broken. configs/example/memtest.py: Revamp options. src/cpu/memtest/memtest.cc: No need for memory initialization. No need to make atomic response... memory system should do that now. src/cpu/memtest/memtest.hh: MemTest really doesn't want to snoop. src/mem/bridge.cc: checkFunctional() cleanup. src/mem/bus.cc: src/mem/bus.hh: src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.cc: src/mem/cache/cache.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_builder.cc: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/coherence_protocol.cc: src/mem/cache/coherence/coherence_protocol.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/miss/SConscript: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr.hh: src/mem/cache/miss/mshr_queue.cc: src/mem/cache/miss/mshr_queue.hh: src/mem/cache/prefetch/base_prefetcher.cc: src/mem/cache/tags/fa_lru.cc: src/mem/cache/tags/fa_lru.hh: src/mem/cache/tags/iic.cc: src/mem/cache/tags/iic.hh: src/mem/cache/tags/lru.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.cc: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.cc: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.cc: src/mem/cache/tags/split_lru.hh: src/mem/packet.cc: src/mem/packet.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/tport.cc: More major reorg. Seems to work for atomic mode now, timing mode still broken. --HG-- extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
2007-05-28Merge vm1.(none):/home/stever/bk/newmem-headSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-cache2 --HG-- extra : convert_revision : 6f462916cb0eb309b6799e94fbf07629abb50eba
2007-05-28Reformat comments to meet line length restriction.Steve Reinhardt
--HG-- extra : convert_revision : 24c00ec4904d9fb4d6e39521e0ff8b8f60d60f6a
2007-05-22Another pass of minor changes in preparation for new protocol.Steve Reinhardt
src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: Get rid of old invalidate propagation logic in preparation for new multilevel snoop protocol. src/mem/cache/coherence/coherence_protocol.cc: L2 cache now has protocol, so protocol must handle ReadExReq coming in from the CPU side. src/mem/cache/miss/mshr_queue.cc: Assertion is failing, so let's take it out for now. src/mem/packet.cc: src/mem/packet.hh: Add WritebackAck command. Reorganize enum to put responses next to corresponding requests. Get rid of unused WriteReqNoAck. --HG-- extra : convert_revision : 24c519846d161978123f9aa029ae358a41546c73
2007-05-18First set of changes for reorganized cache coherence support.Steve Reinhardt
Compiles but doesn't work... committing just so I can merge (stupid bk!). src/mem/bridge.cc: Get rid of SNOOP_COMMIT. src/mem/bus.cc: src/mem/packet.hh: Get rid of SNOOP_COMMIT & two-pass snoop. First bits of EXPRESS_SNOOP support. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/miss/miss_queue.cc: src/mem/cache/prefetch/base_prefetcher.cc: Big reorg of ports and port-related functions & events. src/mem/cache/cache.cc: src/mem/cache/cache_builder.cc: src/mem/cache/coherence/SConscript: Get rid of UniCoherence object. --HG-- extra : convert_revision : 7672434fa3115c9b1c94686f497e57e90413b7c3
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
directly configured by python. Move stuff from root.(cc|hh) to core.(cc|hh) since it really belogs there now. In the process, simplify how ticks are used in the python code. --HG-- extra : convert_revision : cf82ee1ea20f9343924f30bacc2a38d4edee8df3
2007-02-12rename store conditional stuff as extra data so it can be used for ↵Ali Saidi
conditional swaps as well Add support for a twin 64 bit int load Add Memory barrier and write barrier flags as appropriate Make atomic memory ops atomic src/arch/alpha/isa/mem.isa: src/arch/alpha/locked_mem.hh: src/cpu/base_dyn_inst.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: rename store conditional stuff as extra data so it can be used for conditional swaps as well src/arch/alpha/types.hh: src/arch/mips/types.hh: src/arch/sparc/types.hh: add a largest read data type for statically allocating read buffers in atomic simple cpu src/arch/isa_parser.py: Add support for a twin 64 bit int load src/arch/sparc/isa/decoder.isa: Make atomic memory ops atomic Add Memory barrier and write barrier flags as appropriate src/arch/sparc/isa/formats/mem/basicmem.isa: add post access code block and define a twinload format for twin loads src/arch/sparc/isa/formats/mem/blockmem.isa: remove old microcoded twin load coad src/arch/sparc/isa/formats/mem/mem.isa: swap.isa replaces the code in loadstore.isa src/arch/sparc/isa/formats/mem/util.isa: add a post access code block src/arch/sparc/isa/includes.isa: need bigint.hh for Twin64_t src/arch/sparc/isa/operands.isa: add a twin 64 int type src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: add support for twinloads add support for swap and conditional swap instructions rename store conditional stuff as extra data so it can be used for conditional swaps as well src/mem/packet.cc: src/mem/packet.hh: Add support for atomic swap memory commands src/mem/packet_access.hh: Add endian conversion function for Twin64_t type src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: Add support for atomic swap memory commands Rename sc code to extradata --HG-- extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
2007-02-07Merge zizzer.eecs.umich.edu:/bk/newmemSteve Reinhardt
into vm1.(none):/home/stever/bk/newmem-head --HG-- extra : convert_revision : c2350e01a052114a264f26551b13fca03a835c61
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
Created MemCmd class to wrap enum and provide handy methods to check attributes, convert to string/int, etc. --HG-- extra : convert_revision : 57f147ad893443e3a2040c6d5b4cdb1a8033930b
2007-02-06Include compiler.hh since we use some of the #definesNathan Binkert
--HG-- extra : convert_revision : 1040addcf3f52d8d9fed2930890dadf524205af9
2007-01-27While I'm waiting for legion to run make m5 compile with a few more compilersAli Saidi
SConstruct: src/SConscript: Add flags for Intel CC while i'm at it src/base/compiler.hh: the _Pragma stuff needst to be called this way unless someone happens to have a cleaner way src/base/cprintf_formats.hh: add std:: where appropriate src/base/statistics.hh: use this->map since icc was getting confused about std::map vs the locally defined map src/cpu/static_inst.hh: Add some more dummy returns where needed src/mem/packet.hh: add more dummy returns where needed src/sim/host.hh: use limits to come up with max tick --HG-- extra : convert_revision : 08e9f7898b29fb9d063136529afb9b6abceab60c
2006-11-14Fix bugs around uni-coherence invalidates being propogated properly.Ron Dreslinski
src/mem/bus.cc: Make it so that invalidates being sent from the responder up don't call the responder but they should also not Panic. src/mem/packet.hh: If we don't have data in the packet, don't call deleteData: Example: InvalidateRequests never have data. --HG-- extra : convert_revision : 18766bc9f3bb4d852ac651d094254d347abd1634
2006-11-12Fix functional access errors related to delayed respnoses in cachePortRon Dreslinski
src/mem/cache/base_cache.cc: On a delayed response, be sure to call the fixPacket wrapper to toggle hasData flag. src/mem/packet.cc: src/mem/packet.hh: Create a wrapper to toggle the hasData flag on delayed responses --HG-- extra : convert_revision : 1ced8d4e3dc12a059fb7636d59e429cd3dd46901
2006-10-21Small bug fixes for timing LL/SC. Better now butSteve Reinhardt
not necessarily 100% there yet. src/mem/cache/cache_impl.hh: Generate response packet on failed store conditional. src/mem/packet.hh: Clear packet flags when reinitializing. (SATISFIED in particular is one we don't want to leave set.) --HG-- extra : convert_revision : 29207c8a09afcbce43f41c480ad0c1b21d47454f
2006-10-21Fix formatting that got screwed up when tabs were removed.Steve Reinhardt
--HG-- extra : convert_revision : 98596542a5774fe010e25632836ce92b66779f53
2006-10-20Use PacketPtr everywhereNathan Binkert
--HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
2006-10-19refactor code for the packet, get rid of packet_impl.hhNathan Binkert
and call it packet_access.hh and fix the #includes so things compile right. --HG-- extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
2006-10-18Fix WriteInvalidateRespRon Dreslinski
--HG-- extra : convert_revision : ac4281944202a9a2f166b305a1eaea507e484bcc
2006-10-13Fix for DMA's in FS caches.Ron Dreslinski
Fix CSHR's for flow control. Fix for Bus Bridges reusing packets (clean flags up) Now both timing/atomic caches with MOESI in UP fail at same point. src/dev/io_device.hh: DMA's should send WriteInvalidates src/mem/bridge.cc: Reusing packet, clean flags in the packet set by bus. src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: src/mem/cache/coherence/simple_coherence.hh: src/mem/cache/coherence/uni_coherence.cc: src/mem/cache/coherence/uni_coherence.hh: Fix CSHR's for flow control. src/mem/packet.hh: Make a writeInvalidateResp, since the DMA expects responses to it's writes --HG-- extra : convert_revision : 59fd6658bcc0d076f4b143169caca946472a86cd
2006-10-12Merge zizzer:/bk/newmemAli Saidi
into zeep.pool:/z/saidi/work/m5.newmem.head src/mem/packet.hh: hand merge --HG-- extra : convert_revision : 3f77707360235dc98c6b12a0367ca64a401313df
2006-10-12add a traceflag for functional accessesAli Saidi
implement fix packet and add the ability to print a packet to a ostream remove tabs in packet.hh (Could people stop inserting them??!?!?!) mark const functions in packet.hh as such src/base/traceflags.py: add a traceflag for functional accesses src/mem/packet.cc: implement fix packet and add the ability to print a packet to a ostream src/mem/packet.hh: add the ability to print a packet to an ostream remove tabs in file mark const functions as such --HG-- extra : convert_revision : 4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
2006-10-11Update for Atomic Coherece with Gabes busRon Dreslinski
--HG-- extra : convert_revision : 6a23052056d1c61cba0a4c77f1030cee419c6fa3
2006-10-10Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus --HG-- extra : convert_revision : 6027c395af044858465eafd3ea78bcfe4c923bcc
2006-10-10Yet another fix to the HasData command attribute.Ron Dreslinski
--HG-- extra : convert_revision : dcf0d7eafa5168591c2b374b452821ca34dde7f9
2006-10-10Actually set the HasData attribute on Read ResponsesRon Dreslinski
--HG-- extra : convert_revision : 129dadbf8091ab00fb7f16eace59df265fc3718c
2006-10-10Fix another merge issueRon Dreslinski
--HG-- extra : convert_revision : 2b33da5e8578ea6a8bdd2d89f183c2e6b942b0fc
2006-10-10Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest src/mem/packet.hh: Hand merge code --HG-- extra : convert_revision : d659418f24f4f4bf9867fec8573a5d227c0dfcea
2006-10-10Fix several bugs pertaining to upgrades/mem leaks.Ron Dreslinski
src/mem/cache/base_cache.cc: Fix a bug about not having a request to send src/mem/cache/base_cache.hh: Fix a bug with the blocking code src/mem/cache/cache.hh: AFix a bug with snoop hits in WB buffer src/mem/cache/cache_impl.hh: Fix a bug with snoop hits in WB buffer Also, add better DPRINTF's src/mem/cache/miss/miss_queue.cc: Fix a bug with upgrades (Need to clean it up later) src/mem/cache/miss/mshr.cc: Fix a memory leak bug, still some outstanding with writebacks not being deleted src/mem/cache/miss/mshr_queue.cc: Fix a bug about upgrades (need to clean up later) src/mem/packet.hh: Fix for newly added cmd attribute for upgrades tests/configs/memtest.py: More interesting testcase --HG-- extra : convert_revision : fcb4f17dd58b537bb4f67a8c835f50e455e8c688
2006-10-09Fixes to the bus, and added fields to the packet.Gabe Black
src/mem/bus.cc: Put back the check to see if the bus is busy. Also, populate the fields in the packet to indicate when the first word and the entire packet will be delivered. src/mem/bus.hh: Remove the occupyBus function. src/mem/packet.hh: Added fields to the packet to indicate when the first chunk of a packet arrives, and when the entire packet arrives. --HG-- extra : convert_revision : cfc7670a33913d48a04d02c6d2448290a51f2d3c
2006-10-09Handle NACK's that occur from devices on the same bus.Ron Dreslinski
Not fully implemented yet, but good enough for single level cache coherence src/mem/packet.hh: Add a bit to distinguish invalidates and upgrades --HG-- extra : convert_revision : 5bf50d535857cea37fbdaf7993915d1332cb757e
2006-10-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus --HG-- extra : convert_revision : 2adde42edead2cedeeba60cc0d2697a2d58682be
2006-10-09Fix a typo preventing compilationRon Dreslinski
--HG-- extra : convert_revision : 9158d81231cd1d083393576744ce80afd0b74867
2006-10-09Fix how upgrades work.Ron Dreslinski
Remove some dead code. src/mem/cache/cache_impl.hh: Upgrades don't need a response. Moved satisfied check into bus so removed some dead code. src/mem/cache/coherence/coherence_protocol.cc: src/mem/packet.hh: Upgrades don't require a response --HG-- extra : convert_revision : dee0440ff19ba4c9e51bf9a47a5b0991265cfc1d
2006-10-08Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus --HG-- extra : convert_revision : 1749397443ccb320d32f8dd23c71ed0431d30cb7
2006-10-08Add in HasData, and move the define of NUM_MEM_CMDS to a more visible location.Gabe Black
--HG-- extra : convert_revision : 4379efe892ca0a39363ee04009e1bbb8c8f77afa
2006-10-05Fixes for functional accesses to use the snoop path.Ron Dreslinski
And small other tweaks to snooping coherence. src/mem/cache/base_cache.hh: Make timing response at the time of send. src/mem/cache/cache.hh: src/mem/cache/cache_impl.hh: Update probe interface to be bi-directional for functional accesses src/mem/packet.hh: Add the function to create an atomic response to a given request --HG-- extra : convert_revision : 04075a117cf30a7df16e6d3ce485543cc77d4ca6
2006-10-05Partial reimplementation of the bus. The "clock" and "width" parameters have ↵Gabe Black
been added, and the HasData flag has been partially added to packets. --HG-- extra : convert_revision : abb2a259fcf843457abbc0bd36f9504fbe6d7d39
2006-08-22Commiting a version of the multi-phase snoop atomic bus so people can see ↵Ron Dreslinski
the framework. Doesn't work, but also doesn't break uni-processor systems. Working on pulling out the changes in the cache so that it remains working. src/mem/bus.cc: Changes for multi-phase snoop Some code for registering snoop ranges (a version that compiles and runs, but does nothing) src/mem/bus.hh: Changes for multi-phase snoop src/mem/packet.hh: Flag for multi-phase snoop src/mem/port.hh: Status for multi-phase snoop --HG-- extra : convert_revision : 4c2e5263bba16e3bcf03aabe36ff45ec36de4720
2006-08-21Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem src/python/m5/objects/BaseCPU.py: Merge duplicate change --HG-- extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16
2006-08-21Changes so that time in the packet is actually set properly.Ron Dreslinski
src/mem/packet.hh: Make sure packets set the time parameter correctly. --HG-- extra : convert_revision : e381d2789e0aaa1b6c2fbde417b7ba5815deec61
2006-08-17Changes to build m5.fastSteve Reinhardt
--HG-- extra : convert_revision : 2ec600b8e72e40e8b96e3b1dbe0334aa05e0f30b
2006-08-16Merge zizzer:/z/m5/Bitkeeper/newmemRon Dreslinski
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : 659f84c883b9992ae48f26c837983b9f8fcf18ab
2006-08-16Fixes for blocking in the caches that needed to be pulledRon Dreslinski
src/mem/cache/base_cache.cc: Add in retry path for blocking with multi-level caches src/mem/cache/base_cache.hh: Pull more of the blocking fixes into head src/mem/packet.hh: Fix typo --HG-- extra : convert_revision : d4d149adfa414136ebd2c4789b739bb065710f7a
2006-08-15fixes for gcc 4.1Ali Saidi
Nate needs to fix sinic builder stuff Gabe needs to verify my fixes to decoder.isa OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset README: Fix the swig version in the readme src/SConscript: remove sinic until nate fixes the builder crap for it src/arch/alpha/system.hh: src/arch/mips/isa/includes.isa: src/arch/sparc/isa/decoder.isa: src/base/stats/visit.cc: src/base/timebuf.hh: src/dev/ide_disk.cc: src/dev/sinic.cc: src/mem/cache/miss/mshr.cc: src/mem/cache/miss/mshr_queue.cc: src/mem/packet.hh: src/mem/request.hh: src/sim/builder.hh: src/sim/system.hh: fixes for gcc 4.1 --HG-- extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
--HG-- extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
2006-07-10Fix offset calculation. Now L2's work with timing&atomic.Ron Dreslinski
src/mem/packet.hh: Offset is based on packet, not request. --HG-- extra : convert_revision : d85af5838370541328ca35072c612d8198020625
2006-07-06Timing cache works for hello world test.Ron Dreslinski
Still need 1) detailed CPU (blocking ability in cache) 1a) Multiple outstanding requests (need to keep track of times for events) 2)Multi-level support 3)MP coherece support 4)LL/SC support 5)Functional path needs to be correctly implemented (temporarily works without multiple outstanding requests (simple cpu)) src/cpu/simple/timing.cc: Temp hack because timing cpu doesn't export ports properly so single I/D cache communicates only through the Icache port. src/mem/cache/base_cache.cc: Handle marking MSHR's in service Add support for getting CSHR's src/mem/cache/base_cache.hh: Make these functions visible at the base cache level src/mem/cache/cache.hh: make the functions virtual src/mem/cache/cache_impl.hh: Rename the function to make sense src/mem/packet.hh: Accidentally clearing the needsResponse field when sending a response back. --HG-- extra : convert_revision : 2325d4e0b77e470fa9da91490317dc8ed88b17e2
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-15 19:43:24 +0000